Altera TSE: Add Altera Ethernet Driver MSGDMA File Components
This patch adds the MSGDMA soft IP support for the Altera Triple Speed Ethernet driver. Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vince Bridgers
David S. Miller
parent
04add4ab7b
commit
94fb0ef4dc
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@ -0,0 +1,202 @@
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/netdevice.h>
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#include "altera_utils.h"
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#include "altera_tse.h"
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#include "altera_msgdmahw.h"
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/* No initialization work to do for MSGDMA */
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int msgdma_initialize(struct altera_tse_private *priv)
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{
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return 0;
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}
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void msgdma_uninitialize(struct altera_tse_private *priv)
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{
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}
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void msgdma_reset(struct altera_tse_private *priv)
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{
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int counter;
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struct msgdma_csr *txcsr =
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(struct msgdma_csr *)priv->tx_dma_csr;
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struct msgdma_csr *rxcsr =
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(struct msgdma_csr *)priv->rx_dma_csr;
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/* Reset Rx mSGDMA */
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iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
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iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control);
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counter = 0;
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while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
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if (tse_bit_is_clear(&rxcsr->status,
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MSGDMA_CSR_STAT_RESETTING))
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break;
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udelay(1);
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}
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if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
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netif_warn(priv, drv, priv->dev,
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"TSE Rx mSGDMA resetting bit never cleared!\n");
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/* clear all status bits */
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iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
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/* Reset Tx mSGDMA */
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iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
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iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control);
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counter = 0;
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while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
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if (tse_bit_is_clear(&txcsr->status,
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MSGDMA_CSR_STAT_RESETTING))
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break;
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udelay(1);
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}
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if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
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netif_warn(priv, drv, priv->dev,
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"TSE Tx mSGDMA resetting bit never cleared!\n");
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/* clear all status bits */
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iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
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}
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void msgdma_disable_rxirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->rx_dma_csr;
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tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_enable_rxirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->rx_dma_csr;
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tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_disable_txirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->tx_dma_csr;
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tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_enable_txirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->tx_dma_csr;
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tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
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}
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void msgdma_clear_rxirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->rx_dma_csr;
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iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
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}
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void msgdma_clear_txirq(struct altera_tse_private *priv)
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{
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struct msgdma_csr *csr = priv->tx_dma_csr;
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iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
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}
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/* return 0 to indicate transmit is pending */
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int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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struct msgdma_extended_desc *desc = priv->tx_dma_desc;
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iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo);
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iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi);
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iowrite32(0, &desc->write_addr_lo);
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iowrite32(0, &desc->write_addr_hi);
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iowrite32(buffer->len, &desc->len);
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iowrite32(0, &desc->burst_seq_num);
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iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride);
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iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
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return 0;
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}
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u32 msgdma_tx_completions(struct altera_tse_private *priv)
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{
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u32 ready = 0;
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u32 inuse;
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u32 status;
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struct msgdma_csr *txcsr =
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(struct msgdma_csr *)priv->tx_dma_csr;
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/* Get number of sent descriptors */
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inuse = ioread32(&txcsr->rw_fill_level) & 0xffff;
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if (inuse) { /* Tx FIFO is not empty */
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ready = priv->tx_prod - priv->tx_cons - inuse - 1;
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} else {
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/* Check for buffered last packet */
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status = ioread32(&txcsr->status);
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if (status & MSGDMA_CSR_STAT_BUSY)
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ready = priv->tx_prod - priv->tx_cons - 1;
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else
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ready = priv->tx_prod - priv->tx_cons;
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}
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return ready;
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}
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/* Put buffer to the mSGDMA RX FIFO
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*/
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int msgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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struct msgdma_extended_desc *desc = priv->rx_dma_desc;
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u32 len = priv->rx_dma_buf_sz;
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dma_addr_t dma_addr = rxbuffer->dma_addr;
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u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
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| MSGDMA_DESC_CTL_END_ON_LEN
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| MSGDMA_DESC_CTL_TR_COMP_IRQ
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| MSGDMA_DESC_CTL_EARLY_IRQ
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| MSGDMA_DESC_CTL_TR_ERR_IRQ
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| MSGDMA_DESC_CTL_GO);
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iowrite32(0, &desc->read_addr_lo);
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iowrite32(0, &desc->read_addr_hi);
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iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo);
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iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi);
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iowrite32(len, &desc->len);
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iowrite32(0, &desc->burst_seq_num);
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iowrite32(0x00010001, &desc->stride);
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iowrite32(control, &desc->control);
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return 1;
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}
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/* status is returned on upper 16 bits,
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* length is returned in lower 16 bits
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*/
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u32 msgdma_rx_status(struct altera_tse_private *priv)
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{
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u32 rxstatus = 0;
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u32 pktlength;
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u32 pktstatus;
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struct msgdma_csr *rxcsr =
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(struct msgdma_csr *)priv->rx_dma_csr;
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struct msgdma_response *rxresp =
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(struct msgdma_response *)priv->rx_dma_resp;
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if (ioread32(&rxcsr->resp_fill_level) & 0xffff) {
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pktlength = ioread32(&rxresp->bytes_transferred);
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pktstatus = ioread32(&rxresp->status);
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rxstatus = pktstatus;
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rxstatus = rxstatus << 16;
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rxstatus |= (pktlength & 0xffff);
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}
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return rxstatus;
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}
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@ -0,0 +1,34 @@
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ALTERA_MSGDMA_H__
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#define __ALTERA_MSGDMA_H__
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void msgdma_reset(struct altera_tse_private *);
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void msgdma_enable_txirq(struct altera_tse_private *);
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void msgdma_enable_rxirq(struct altera_tse_private *);
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void msgdma_disable_rxirq(struct altera_tse_private *);
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void msgdma_disable_txirq(struct altera_tse_private *);
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void msgdma_clear_rxirq(struct altera_tse_private *);
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void msgdma_clear_txirq(struct altera_tse_private *);
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u32 msgdma_tx_completions(struct altera_tse_private *);
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int msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *);
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int msgdma_tx_buffer(struct altera_tse_private *, struct tse_buffer *);
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u32 msgdma_rx_status(struct altera_tse_private *);
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int msgdma_initialize(struct altera_tse_private *);
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void msgdma_uninitialize(struct altera_tse_private *);
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#endif /* __ALTERA_MSGDMA_H__ */
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@ -0,0 +1,167 @@
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ALTERA_MSGDMAHW_H__
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#define __ALTERA_MSGDMAHW_H__
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/* mSGDMA standard descriptor format
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*/
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struct msgdma_desc {
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u32 read_addr; /* data buffer source address */
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u32 write_addr; /* data buffer destination address */
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u32 len; /* the number of bytes to transfer per descriptor */
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u32 control; /* characteristics of the transfer */
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};
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/* mSGDMA extended descriptor format
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*/
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struct msgdma_extended_desc {
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u32 read_addr_lo; /* data buffer source address low bits */
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u32 write_addr_lo; /* data buffer destination address low bits */
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u32 len; /* the number of bytes to transfer
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* per descriptor
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*/
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u32 burst_seq_num; /* bit 31:24 write burst
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* bit 23:16 read burst
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* bit 15:0 sequence number
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*/
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u32 stride; /* bit 31:16 write stride
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* bit 15:0 read stride
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*/
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u32 read_addr_hi; /* data buffer source address high bits */
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u32 write_addr_hi; /* data buffer destination address high bits */
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u32 control; /* characteristics of the transfer */
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};
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/* mSGDMA descriptor control field bit definitions
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*/
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#define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
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#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
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#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
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#define MSGDMA_DESC_CTL_PARK_READS BIT(10)
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#define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
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#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
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#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
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#define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
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#define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
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#define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
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#define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)
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/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
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* descriptor FIFO(s)
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*/
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#define MSGDMA_DESC_CTL_GO BIT(31)
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/* Tx buffer control flags
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*/
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#define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \
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MSGDMA_DESC_CTL_TR_ERR_IRQ | \
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MSGDMA_DESC_CTL_GO)
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#define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_TR_ERR_IRQ | \
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MSGDMA_DESC_CTL_GO)
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#define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \
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MSGDMA_DESC_CTL_TR_ERR_IRQ | \
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MSGDMA_DESC_CTL_GO)
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#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
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MSGDMA_DESC_CTL_GEN_EOP | \
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \
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MSGDMA_DESC_CTL_TR_ERR_IRQ | \
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MSGDMA_DESC_CTL_GO)
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#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
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MSGDMA_DESC_CTL_END_ON_LEN | \
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MSGDMA_DESC_CTL_TR_COMP_IRQ | \
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MSGDMA_DESC_CTL_EARLY_IRQ | \
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MSGDMA_DESC_CTL_TR_ERR_IRQ | \
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MSGDMA_DESC_CTL_GO)
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/* mSGDMA extended descriptor stride definitions
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*/
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#define MSGDMA_DESC_TX_STRIDE (0x00010001)
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#define MSGDMA_DESC_RX_STRIDE (0x00010001)
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/* mSGDMA dispatcher control and status register map
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*/
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struct msgdma_csr {
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u32 status; /* Read/Clear */
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u32 control; /* Read/Write */
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u32 rw_fill_level; /* bit 31:16 - write fill level
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* bit 15:0 - read fill level
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*/
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u32 resp_fill_level; /* bit 15:0 */
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u32 rw_seq_num; /* bit 31:16 - write sequence number
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* bit 15:0 - read sequence number
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*/
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u32 pad[3]; /* reserved */
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};
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/* mSGDMA CSR status register bit definitions
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*/
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#define MSGDMA_CSR_STAT_BUSY BIT(0)
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#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)
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#define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2)
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#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3)
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#define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4)
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#define MSGDMA_CSR_STAT_STOPPED BIT(5)
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#define MSGDMA_CSR_STAT_RESETTING BIT(6)
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#define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7)
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#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)
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#define MSGDMA_CSR_STAT_IRQ BIT(9)
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#define MSGDMA_CSR_STAT_MASK 0x3FF
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#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF
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#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)
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#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)
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#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)
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#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)
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#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)
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#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)
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#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)
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#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)
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#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)
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#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)
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/* mSGDMA CSR control register bit definitions
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*/
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#define MSGDMA_CSR_CTL_STOP BIT(0)
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#define MSGDMA_CSR_CTL_RESET BIT(1)
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#define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2)
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#define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3)
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#define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4)
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#define MSGDMA_CSR_CTL_STOP_DESCS BIT(5)
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/* mSGDMA CSR fill level bits
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*/
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#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
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#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
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#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
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/* mSGDMA response register map
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*/
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struct msgdma_response {
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u32 bytes_transferred;
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u32 status;
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};
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/* mSGDMA response register bit definitions
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*/
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#define MSGDMA_RESP_EARLY_TERM BIT(8)
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#define MSGDMA_RESP_ERR_MASK 0xFF
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||||
|
||||
#endif /* __ALTERA_MSGDMA_H__*/
|
||||
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Reference in New Issue