Fixes for omaps for v4.7-rc cycle:
- Two boot warning fixes from the RCU tree that should have gotten merged several weeks ago already but did not because of issues with who merges them. Paul has now split the RCU warning fixes into sets for various maintainers. - Fix ams-delta FIQ regression caused by omap1 sparse IRQ changes - Fix PM for omap3 boards using timer12 and gptimer, like the original beagleboard - Fix hangs on am437x-sk-evm by lowering the I2C bus speed -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXY8wuAAoJEBvUPslcq6VzGBQQAJ6OIH0Gws19Wyi8IqnjMLJN npu+JXU0xP5bBZ+HbCVjyN8k32drhXdwDMQ+u1DvBYwUuyLIIRZPZF4aHb8fDfOC v1VqUzQRzj1FCh9MlkdqTedA180WCo5PCGlFOon0BmaZlv9WevEaTOYrEgyZPrmk quBnaE+baZfGxWBbDSN+OrGYobQRs7Eu8bel0gh628CDiajrbwlIyAcNdEn5C/Uu GHiEuIQcxb4b62mwAwh/t7el9ureirsS1b6mFB41puPmF/lYawI6YaCWIL48lbMd XsgKGnFDU6dgSO5QRx5PhP/7YP9FetS0U+g7iFhgjmArNCraNQYBY0ltMweOG0qe M8BPxDuCnhm1Q+PcjBORteN/PF47kcnBMpiJVVTmq5JRlXUqXecKpoScCt9HfPgy EJq+esLQNIuRw9cEwVPQBj80GyxFUVqL/Rzo7xjEwTDPYRQERGCB7V68iV25on3w 07dOVl/lSwe902ik580wnlGUq+J09wk+9hIKV2XwQAV/8mKaWMc3pA8rE/efLJoC buAsccxVcEsR3+uLSsU/P+fFm8nfBRmiOO9yIR4gez0BhbiDMc1zpwwhLkI+vTT4 D3PnuUdVeBvoGTNnpwqSURxajhaK0DSKTwhWnWGubYfXd3B48sW76rvKLO1FThgL qyaed06QFeWj8gV+VZLb =P0Vi -----END PGP SIGNATURE----- Merge tag 'fixes-rcu-fiq-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Fixes for omaps for v4.7-rc cycle: - Two boot warning fixes from the RCU tree that should have gotten merged several weeks ago already but did not because of issues with who merges them. Paul has now split the RCU warning fixes into sets for various maintainers. - Fix ams-delta FIQ regression caused by omap1 sparse IRQ changes - Fix PM for omap3 boards using timer12 and gptimer, like the original beagleboard - Fix hangs on am437x-sk-evm by lowering the I2C bus speed * tag 'fixes-rcu-fiq-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am437x-sk-evm: Reduce i2c0 bus speed for tps65218 ARM: OMAP2+: timer: add probe for clocksources ARM: OMAP1: fix ams-delta FIQ handler to work with sparse IRQ arm: Use _rcuidle for smp_cross_call() tracepoints arm: Use _rcuidle tracepoint to allow use from idle Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
9503427e91
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@ -418,7 +418,7 @@ &i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <400000>;
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clock-frequency = <100000>;
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tps@24 {
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compatible = "ti,tps65218";
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@ -486,7 +486,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = {
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static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
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{
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trace_ipi_raise(target, ipi_types[ipinr]);
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trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
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__smp_cross_call(target, ipinr);
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}
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@ -43,8 +43,8 @@
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#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
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/* IRQ handler register bitmasks */
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#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
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#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1)
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#define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
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#define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
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/* Driver buffer byte offsets */
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#define BUF_MASK (FIQ_MASK * 4)
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@ -110,7 +110,7 @@ ENTRY(qwerty_fiqin_start)
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mov r8, #2 @ reset FIQ agreement
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str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
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cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt?
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cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
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beq gpio @ yes - process it
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mov r8, #1
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@ -109,7 +109,8 @@ void __init ams_delta_init_fiq(void)
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* Since no set_type() method is provided by OMAP irq chip,
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* switch to edge triggered interrupt type manually.
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*/
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offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
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offset = IRQ_ILR0_REG_OFFSET +
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((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
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val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
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omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
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@ -149,7 +150,7 @@ void __init ams_delta_init_fiq(void)
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/*
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* Redirect GPIO interrupts to FIQ
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*/
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offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
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offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
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val = omap_readl(OMAP_IH1_BASE + offset) | 1;
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omap_writel(val, OMAP_IH1_BASE + offset);
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}
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@ -14,6 +14,8 @@
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#ifndef __AMS_DELTA_FIQ_H
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#define __AMS_DELTA_FIQ_H
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#include <mach/irqs.h>
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/*
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* Interrupt number used for passing control from FIQ to IRQ.
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* IRQ12, described as reserved, has been selected.
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@ -186,8 +186,9 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
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trace_state = (PWRDM_TRACE_STATES_FLAG |
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((next & OMAP_POWERSTATE_MASK) << 8) |
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((prev & OMAP_POWERSTATE_MASK) << 0));
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trace_power_domain_target(pwrdm->name, trace_state,
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smp_processor_id());
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trace_power_domain_target_rcuidle(pwrdm->name,
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trace_state,
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smp_processor_id());
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}
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break;
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default:
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@ -523,8 +524,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
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/* Trace the pwrdm desired target state */
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trace_power_domain_target(pwrdm->name, pwrst,
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smp_processor_id());
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trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
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smp_processor_id());
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/* Program the pwrdm desired target state */
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ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
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}
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@ -496,8 +496,7 @@ void __init omap_init_time(void)
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__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
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2, "timer_sys_ck", NULL, false);
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if (of_have_populated_dt())
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clocksource_probe();
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clocksource_probe();
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}
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
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@ -505,6 +504,8 @@ void __init omap3_secure_sync32k_timer_init(void)
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{
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__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
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2, "timer_sys_ck", NULL, false);
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clocksource_probe();
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}
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#endif /* CONFIG_ARCH_OMAP3 */
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@ -513,6 +514,8 @@ void __init omap3_gptimer_timer_init(void)
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{
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__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
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1, "timer_sys_ck", "ti,timer-alwon", true);
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clocksource_probe();
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}
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#endif
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