dmaengine: stm32-dma: threshold manages with bitfield feature
>From now on, DMA bitfield is to manage DMA FIFO Threshold. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -116,6 +116,10 @@
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#define STM32_DMA_MAX_DATA_PARAM 0x03
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#define STM32_DMA_MAX_BURST 16
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/* DMA Features */
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#define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
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#define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
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enum stm32_dma_width {
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STM32_DMA_BYTE,
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STM32_DMA_HALF_WORD,
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@ -129,11 +133,18 @@ enum stm32_dma_burst_size {
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STM32_DMA_BURST_INCR16,
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};
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/**
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* struct stm32_dma_cfg - STM32 DMA custom configuration
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* @channel_id: channel ID
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* @request_line: DMA request
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* @stream_config: 32bit mask specifying the DMA channel configuration
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* @features: 32bit mask specifying the DMA Feature list
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*/
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struct stm32_dma_cfg {
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u32 channel_id;
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u32 request_line;
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u32 stream_config;
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u32 threshold;
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u32 features;
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};
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struct stm32_dma_chan_reg {
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@ -171,6 +182,7 @@ struct stm32_dma_chan {
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u32 next_sg;
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struct dma_slave_config dma_sconfig;
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struct stm32_dma_chan_reg chan_reg;
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u32 threshold;
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};
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struct stm32_dma_device {
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@ -976,7 +988,8 @@ static void stm32_dma_set_config(struct stm32_dma_chan *chan,
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/* Enable Interrupts */
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chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
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chan->chan_reg.dma_sfcr = cfg->threshold & STM32_DMA_SFCR_FTH_MASK;
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chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
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chan->chan_reg.dma_sfcr = STM32_DMA_SFCR_FTH(chan->threshold);
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}
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static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
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@ -996,7 +1009,7 @@ static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
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cfg.channel_id = dma_spec->args[0];
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cfg.request_line = dma_spec->args[1];
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cfg.stream_config = dma_spec->args[2];
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cfg.threshold = dma_spec->args[3];
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cfg.features = dma_spec->args[3];
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if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
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(cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
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