drm/i915/perf: enable perf support on CNL
This adds new registers to the whitelist to configs emitted from userspace. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171110190845.32574-6-lionel.g.landwerlin@intel.com
This commit is contained in:
Lionel Landwerlin
parent
5888576b0b
commit
95690a02fb
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@ -163,7 +163,8 @@ i915-y += i915_perf.o \
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i915_oa_kblgt3.o \
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i915_oa_glk.o \
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i915_oa_cflgt2.o \
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i915_oa_cflgt3.o
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i915_oa_cflgt3.o \
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i915_oa_cnl.o
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ifeq ($(CONFIG_DRM_I915_GVT),y)
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i915-y += intel_gvt.o
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@ -0,0 +1,121 @@
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/*
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* Autogenerated file by GPU Top : https://github.com/rib/gputop
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* DO NOT EDIT manually!
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*
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*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/sysfs.h>
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#include "i915_drv.h"
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#include "i915_oa_cnl.h"
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static const struct i915_oa_reg b_counter_config_test_oa[] = {
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{ _MMIO(0x2740), 0x00000000 },
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{ _MMIO(0x2710), 0x00000000 },
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{ _MMIO(0x2714), 0xf0800000 },
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{ _MMIO(0x2720), 0x00000000 },
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{ _MMIO(0x2724), 0xf0800000 },
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{ _MMIO(0x2770), 0x00000004 },
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{ _MMIO(0x2774), 0x0000ffff },
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{ _MMIO(0x2778), 0x00000003 },
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{ _MMIO(0x277c), 0x0000ffff },
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{ _MMIO(0x2780), 0x00000007 },
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{ _MMIO(0x2784), 0x0000ffff },
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{ _MMIO(0x2788), 0x00100002 },
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{ _MMIO(0x278c), 0x0000fff7 },
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{ _MMIO(0x2790), 0x00100002 },
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{ _MMIO(0x2794), 0x0000ffcf },
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{ _MMIO(0x2798), 0x00100082 },
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{ _MMIO(0x279c), 0x0000ffef },
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{ _MMIO(0x27a0), 0x001000c2 },
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{ _MMIO(0x27a4), 0x0000ffe7 },
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{ _MMIO(0x27a8), 0x00100001 },
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{ _MMIO(0x27ac), 0x0000ffe7 },
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};
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static const struct i915_oa_reg flex_eu_config_test_oa[] = {
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};
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static const struct i915_oa_reg mux_config_test_oa[] = {
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{ _MMIO(0xd04), 0x00000200 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x17060000 },
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{ _MMIO(0x9840), 0x00000000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x13034000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x07060066 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x05060000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x0f080040 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x07091000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x0f041000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x1d004000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x35000000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x49000000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x3d000000 },
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{ _MMIO(0x9884), 0x00000007 },
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{ _MMIO(0x9888), 0x31000000 },
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};
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static ssize_t
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show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "1\n");
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}
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void
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i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
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{
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strncpy(dev_priv->perf.oa.test_config.uuid,
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"db41edd4-d8e7-4730-ad11-b9a2d6833503",
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UUID_STRING_LEN);
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dev_priv->perf.oa.test_config.id = 1;
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dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
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dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
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dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
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dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
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dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
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dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
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dev_priv->perf.oa.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
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dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
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dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
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dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
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dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
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dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
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}
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@ -0,0 +1,34 @@
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/*
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* Autogenerated file by GPU Top : https://github.com/rib/gputop
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* DO NOT EDIT manually!
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*
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*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef __I915_OA_CNL_H__
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#define __I915_OA_CNL_H__
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extern void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv);
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#endif
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@ -208,6 +208,7 @@
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#include "i915_oa_glk.h"
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#include "i915_oa_cflgt2.h"
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#include "i915_oa_cflgt3.h"
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#include "i915_oa_cnl.h"
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/* HW requires this to be a power of two, between 128k and 16M, though driver
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* is currently generally designed assuming the largest 16M size is used such
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@ -1852,7 +1853,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
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* be read back from automatically triggered reports, as part of the
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* RPT_ID field.
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*/
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if (IS_GEN9(dev_priv)) {
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if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
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I915_WRITE(GEN8_OA_DEBUG,
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_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
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GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
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@ -1885,6 +1886,16 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
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}
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static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
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{
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/* Reset all contexts' slices/subslices configurations. */
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gen8_configure_all_contexts(dev_priv, NULL, false);
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/* Make sure we disable noa to save power. */
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I915_WRITE(RPM_CONFIG1,
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I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
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}
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static void gen7_oa_enable(struct drm_i915_private *dev_priv)
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{
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/*
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@ -2937,6 +2948,8 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
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i915_perf_load_test_config_cflgt2(dev_priv);
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if (IS_CFL_GT3(dev_priv))
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i915_perf_load_test_config_cflgt3(dev_priv);
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} else if (IS_CANNONLAKE(dev_priv)) {
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i915_perf_load_test_config_cnl(dev_priv);
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}
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if (dev_priv->perf.oa.test_config.id == 0)
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@ -3022,6 +3035,12 @@ static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
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(addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg);
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}
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static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
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{
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return gen8_is_valid_mux_addr(dev_priv, addr) ||
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(addr >= OA_PERFCNT3_LO.reg && addr <= OA_PERFCNT4_HI.reg);
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}
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static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
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{
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return gen7_is_valid_mux_addr(dev_priv, addr) ||
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@ -3475,6 +3494,26 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
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default:
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break;
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}
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} else if (IS_GEN10(dev_priv)) {
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dev_priv->perf.oa.ops.is_valid_b_counter_reg =
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gen7_is_valid_b_counter_addr;
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dev_priv->perf.oa.ops.is_valid_mux_reg =
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gen10_is_valid_mux_addr;
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dev_priv->perf.oa.ops.is_valid_flex_reg =
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gen8_is_valid_flex_addr;
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dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
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dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
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dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
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dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
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dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
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/* Default frequency, although we need to read it from
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* the register as it might vary between parts.
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*/
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dev_priv->perf.oa.timestamp_frequency = 12000000;
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}
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}
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@ -1106,6 +1106,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define OA_PERFCNT1_HI _MMIO(0x91BC)
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#define OA_PERFCNT2_LO _MMIO(0x91C0)
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#define OA_PERFCNT2_HI _MMIO(0x91C4)
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#define OA_PERFCNT3_LO _MMIO(0x91C8)
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#define OA_PERFCNT3_HI _MMIO(0x91CC)
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#define OA_PERFCNT4_LO _MMIO(0x91D8)
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#define OA_PERFCNT4_HI _MMIO(0x91DC)
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#define OA_PERFMATRIX_LO _MMIO(0x91C8)
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#define OA_PERFMATRIX_HI _MMIO(0x91CC)
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@ -1113,6 +1117,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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/* RPM unit config (Gen8+) */
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#define RPM_CONFIG0 _MMIO(0x0D00)
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#define RPM_CONFIG1 _MMIO(0x0D04)
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#define GEN10_GT_NOA_ENABLE (1 << 9)
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/* RCP unit config (Gen8+) */
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#define RCP_CONFIG _MMIO(0x0D08)
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