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ARM: dts: r8a7794: add MSTP10 clocks 

Add MSTP10 clocks to the R8A7794 device tree.

This patch is based on the commit ee9141522d ("ARM: shmobile: r8a7791:
add MSTP10 support on DTSI").

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Sergei Shtylyov 2016-07-27 14:01:01 -07:00 committed by Simon Horman
parent 2a29f9d6fe
commit 975fb77f87
2 changed files with 76 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -1267,6 +1267,58 @@ R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
}; };
mstp10_clks: mstp10_clks@e6150998 {
compatible = "renesas,r8a7794-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
<&mstp10_clks R8A7794_CLK_SCU_ALL>;
#clock-cells = <1>;
clock-indices = <R8A7794_CLK_SSI_ALL
R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
R8A7794_CLK_SCU_ALL
R8A7794_CLK_SCU_DVC1
R8A7794_CLK_SCU_DVC0
R8A7794_CLK_SCU_CTU1_MIX1
R8A7794_CLK_SCU_CTU0_MIX0
R8A7794_CLK_SCU_SRC6
R8A7794_CLK_SCU_SRC5
R8A7794_CLK_SCU_SRC4
R8A7794_CLK_SCU_SRC3
R8A7794_CLK_SCU_SRC2
R8A7794_CLK_SCU_SRC1>;
clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
"ssi6", "ssi5", "ssi4", "ssi3",
"ssi2", "ssi1", "ssi0",
"scu-all", "scu-dvc1", "scu-dvc0",
"scu-ctu1-mix1", "scu-ctu0-mix0",
"scu-src6", "scu-src5", "scu-src4",
"scu-src3", "scu-src2", "scu-src1";
};
mstp11_clks: mstp11_clks@e615099c { mstp11_clks: mstp11_clks@e615099c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;

24
include/dt-bindings/clock/r8a7794-clock.h
View File

@ -108,6 +108,30 @@
#define R8A7794_CLK_I2C1 30 #define R8A7794_CLK_I2C1 30
#define R8A7794_CLK_I2C0 31 #define R8A7794_CLK_I2C0 31
/* MSTP10 */
#define R8A7794_CLK_SSI_ALL 5
#define R8A7794_CLK_SSI9 6
#define R8A7794_CLK_SSI8 7
#define R8A7794_CLK_SSI7 8
#define R8A7794_CLK_SSI6 9
#define R8A7794_CLK_SSI5 10
#define R8A7794_CLK_SSI4 11
#define R8A7794_CLK_SSI3 12
#define R8A7794_CLK_SSI2 13
#define R8A7794_CLK_SSI1 14
#define R8A7794_CLK_SSI0 15
#define R8A7794_CLK_SCU_ALL 17
#define R8A7794_CLK_SCU_DVC1 18
#define R8A7794_CLK_SCU_DVC0 19
#define R8A7794_CLK_SCU_CTU1_MIX1 20
#define R8A7794_CLK_SCU_CTU0_MIX0 21
#define R8A7794_CLK_SCU_SRC6 25
#define R8A7794_CLK_SCU_SRC5 26
#define R8A7794_CLK_SCU_SRC4 27
#define R8A7794_CLK_SCU_SRC3 28
#define R8A7794_CLK_SCU_SRC2 29
#define R8A7794_CLK_SCU_SRC1 30
/* MSTP11 */ /* MSTP11 */
#define R8A7794_CLK_SCIFA3 6 #define R8A7794_CLK_SCIFA3 6
#define R8A7794_CLK_SCIFA4 7 #define R8A7794_CLK_SCIFA4 7