Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: efm32gg: Pass correct type to hw provider registration clk: berlin: Pass correct type to hw provider registration clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
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977f0ab058
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@ -685,7 +685,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
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}
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/* register clk-provider */
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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return;
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@ -382,7 +382,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
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}
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/* register clk-provider */
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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return;
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@ -82,6 +82,6 @@ static void __init efm32gg_cmu_init(struct device_node *np)
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hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
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@ -191,6 +191,8 @@ static struct clk_div_table axi_div_table[] = {
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static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
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0x050, 0, 3, axi_div_table, 0);
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#define SUN6I_A31_AHB1_REG 0x054
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static const char * const ahb1_parents[] = { "osc32k", "osc24M",
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"axi", "pll-periph" };
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@ -1230,6 +1232,16 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
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val &= BIT(16);
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writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
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/* Force AHB1 to PLL6 / 3 */
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val = readl(reg + SUN6I_A31_AHB1_REG);
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/* set PLL6 pre-div = 3 */
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val &= ~GENMASK(7, 6);
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val |= 0x2 << 6;
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/* select PLL6 / pre-div */
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val &= ~GENMASK(13, 12);
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val |= 0x3 << 12;
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writel(val, reg + SUN6I_A31_AHB1_REG);
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sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
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ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
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@ -373,7 +373,7 @@ static void sun4i_get_apb1_factors(struct factors_request *req)
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else
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calcp = 3;
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calcm = (req->parent_rate >> calcp) - 1;
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calcm = (div >> calcp) - 1;
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req->rate = (req->parent_rate >> calcp) / (calcm + 1);
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req->m = calcm;
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