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ASoC: rt5682: Add a property for DMIC clock rate 

The patch adds a property for DMIC clock rate (hz) and changes the
default to the common optimize DMIC clock rate.

Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Link: https://lore.kernel.org/r/20200323082547.7898-1-oder_chiou@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Oder Chiou 2020-03-23 16:25:45 +08:00 committed by Mark Brown
parent bc765162f7
commit 9a74c44a6f
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 8 additions and 2 deletions
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1
include/sound/rt5682.h
View File

@ -38,6 +38,7 @@ struct rt5682_platform_data {
enum rt5682_dmic1_clk_pin dmic1_clk_pin;
enum rt5682_jd_src jd_src;
unsigned int btndet_delay;
unsigned int dmic_clk_rate;
const char *dai_clk_names[RT5682_DAI_NUM_CLKS];
};

9
sound/soc/codecs/rt5682.c
View File

@ -1231,10 +1231,13 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
int idx = -EINVAL;
int idx = -EINVAL, dmic_clk_rate = 3072000;
static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
if (rt5682->pdata.dmic_clk_rate)
dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
@ -3231,6 +3234,8 @@ static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
&rt5682->pdata.jd_src);
device_property_read_u32(dev, "realtek,btndet-delay",
&rt5682->pdata.btndet_delay);
device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
&rt5682->pdata.dmic_clk_rate);
rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
"realtek,ldo1-en-gpios", 0);