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crypto: hisilicon/hpre - add algorithm type 

Algorithm type is brought in to get hardware HPRE queue
to support different algorithms.

Signed-off-by: Meng Yu <yumeng18@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Meng Yu 2021-03-04 14:35:45 +08:00 committed by Herbert Xu
parent 8123455a64
commit 9b94ae7290
3 changed files with 24 additions and 9 deletions
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10
drivers/crypto/hisilicon/hpre/hpre.h
View File

@ -10,6 +10,14 @@
#define HPRE_PF_DEF_Q_NUM 64 #define HPRE_PF_DEF_Q_NUM 64
#define HPRE_PF_DEF_Q_BASE 0 #define HPRE_PF_DEF_Q_BASE 0
/*
* type used in qm sqc DW6.
* 0 - Algorithm which has been supported in V2, like RSA, DH and so on;
* 1 - ECC algorithm in V3.
*/
#define HPRE_V2_ALG_TYPE 0
#define HPRE_V3_ECC_ALG_TYPE 1
enum { enum {
HPRE_CLUSTER0, HPRE_CLUSTER0,
HPRE_CLUSTER1, HPRE_CLUSTER1,
@ -92,7 +100,7 @@ struct hpre_sqe {
__le32 rsvd1[_HPRE_SQE_ALIGN_EXT]; __le32 rsvd1[_HPRE_SQE_ALIGN_EXT];
}; };
struct hisi_qp *hpre_create_qp(void); struct hisi_qp *hpre_create_qp(u8 type);
int hpre_algs_register(struct hisi_qm *qm); int hpre_algs_register(struct hisi_qm *qm);
void hpre_algs_unregister(struct hisi_qm *qm); void hpre_algs_unregister(struct hisi_qm *qm);

12
drivers/crypto/hisilicon/hpre/hpre_crypto.c
View File

@ -152,12 +152,12 @@ static void hpre_rm_req_from_ctx(struct hpre_asym_request *hpre_req)
} }
} }
static struct hisi_qp *hpre_get_qp_and_start(void) static struct hisi_qp *hpre_get_qp_and_start(u8 type)
{ {
struct hisi_qp *qp; struct hisi_qp *qp;
int ret; int ret;
qp = hpre_create_qp(); qp = hpre_create_qp(type);
if (!qp) { if (!qp) {
pr_err("Can not create hpre qp!\n"); pr_err("Can not create hpre qp!\n");
return ERR_PTR(-ENODEV); return ERR_PTR(-ENODEV);
@ -422,11 +422,11 @@ static void hpre_alg_cb(struct hisi_qp *qp, void *resp)
req->cb(ctx, resp); req->cb(ctx, resp);
} }
static int hpre_ctx_init(struct hpre_ctx *ctx) static int hpre_ctx_init(struct hpre_ctx *ctx, u8 type)
{ {
struct hisi_qp *qp; struct hisi_qp *qp;
qp = hpre_get_qp_and_start(); qp = hpre_get_qp_and_start(type);
if (IS_ERR(qp)) if (IS_ERR(qp))
return PTR_ERR(qp); return PTR_ERR(qp);
@ -674,7 +674,7 @@ static int hpre_dh_init_tfm(struct crypto_kpp *tfm)
{ {
struct hpre_ctx *ctx = kpp_tfm_ctx(tfm); struct hpre_ctx *ctx = kpp_tfm_ctx(tfm);
return hpre_ctx_init(ctx); return hpre_ctx_init(ctx, HPRE_V2_ALG_TYPE);
} }
static void hpre_dh_exit_tfm(struct crypto_kpp *tfm) static void hpre_dh_exit_tfm(struct crypto_kpp *tfm)
@ -1100,7 +1100,7 @@ static int hpre_rsa_init_tfm(struct crypto_akcipher *tfm)
return PTR_ERR(ctx->rsa.soft_tfm); return PTR_ERR(ctx->rsa.soft_tfm);
} }
ret = hpre_ctx_init(ctx); ret = hpre_ctx_init(ctx, HPRE_V2_ALG_TYPE);
if (ret) if (ret)
crypto_free_akcipher(ctx->rsa.soft_tfm); crypto_free_akcipher(ctx->rsa.soft_tfm);

11
drivers/crypto/hisilicon/hpre/hpre_main.c
View File

@ -226,13 +226,20 @@ static u32 vfs_num;
module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
struct hisi_qp *hpre_create_qp(void) struct hisi_qp *hpre_create_qp(u8 type)
{ {
int node = cpu_to_node(smp_processor_id()); int node = cpu_to_node(smp_processor_id());
struct hisi_qp *qp = NULL; struct hisi_qp *qp = NULL;
int ret; int ret;
ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, 0, node, &qp); if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE)
return NULL;
/*
* type: 0 - RSA/DH. algorithm supported in V2,
* 1 - ECC algorithm in V3.
*/
ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp);
if (!ret) if (!ret)
return qp; return qp;