iio: adc: stm32-adc: add power management support
Add support for runtime PM & sleep. Move all regulator and clock management to dedicated HW start/stop routines. Then rely on (runtime) PM OPS to call them. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Fabrice Gasnier
Jonathan Cameron
parent
0da98c7b28
commit
9bdbb1139c
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@ -16,6 +16,7 @@
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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@ -48,15 +49,19 @@
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#define STM32H7_CKMODE_SHIFT 16
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
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/**
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* stm32_adc_common_regs - stm32 common registers, compatible dependent data
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* @csr: common status register offset
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* @ccr: common control register offset
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* @eoc1: adc1 end of conversion flag in @csr
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* @eoc2: adc2 end of conversion flag in @csr
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* @eoc3: adc3 end of conversion flag in @csr
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*/
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struct stm32_adc_common_regs {
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u32 csr;
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u32 ccr;
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u32 eoc1_msk;
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u32 eoc2_msk;
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u32 eoc3_msk;
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@ -85,6 +90,7 @@ struct stm32_adc_priv_cfg {
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* @vref: regulator reference
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* @cfg: compatible configuration data
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* @common: common data for all ADC instances
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* @ccr_bak: backup CCR in low power mode
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*/
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struct stm32_adc_priv {
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int irq[STM32_ADC_MAX_ADCS];
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@ -94,6 +100,7 @@ struct stm32_adc_priv {
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struct regulator *vref;
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const struct stm32_adc_priv_cfg *cfg;
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struct stm32_adc_common common;
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u32 ccr_bak;
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};
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static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
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@ -265,6 +272,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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/* STM32F4 common registers definitions */
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static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.csr = STM32F4_ADC_CSR,
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.ccr = STM32F4_ADC_CCR,
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.eoc1_msk = STM32F4_EOC1,
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.eoc2_msk = STM32F4_EOC2,
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.eoc3_msk = STM32F4_EOC3,
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@ -273,6 +281,7 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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/* STM32H7 common registers definitions */
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static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
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.csr = STM32H7_ADC_CSR,
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.ccr = STM32H7_ADC_CCR,
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.eoc1_msk = STM32H7_EOC_MST,
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.eoc2_msk = STM32H7_EOC_SLV,
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};
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@ -379,6 +388,61 @@ static void stm32_adc_irq_remove(struct platform_device *pdev,
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}
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}
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static int stm32_adc_core_hw_start(struct device *dev)
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{
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struct stm32_adc_common *common = dev_get_drvdata(dev);
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struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
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int ret;
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ret = regulator_enable(priv->vref);
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if (ret < 0) {
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dev_err(dev, "vref enable failed\n");
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return ret;
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}
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if (priv->bclk) {
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ret = clk_prepare_enable(priv->bclk);
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if (ret < 0) {
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dev_err(dev, "bus clk enable failed\n");
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goto err_regulator_disable;
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}
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}
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if (priv->aclk) {
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ret = clk_prepare_enable(priv->aclk);
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if (ret < 0) {
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dev_err(dev, "adc clk enable failed\n");
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goto err_bclk_disable;
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}
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}
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writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
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return 0;
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err_bclk_disable:
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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err_regulator_disable:
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regulator_disable(priv->vref);
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return ret;
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}
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static void stm32_adc_core_hw_stop(struct device *dev)
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{
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struct stm32_adc_common *common = dev_get_drvdata(dev);
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struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
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/* Backup CCR that may be lost (depends on power state to achieve) */
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priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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regulator_disable(priv->vref);
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}
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static int stm32_adc_probe(struct platform_device *pdev)
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{
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struct stm32_adc_priv *priv;
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@ -393,6 +457,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, &priv->common);
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priv->cfg = (const struct stm32_adc_priv_cfg *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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@ -410,67 +475,51 @@ static int stm32_adc_probe(struct platform_device *pdev)
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return ret;
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}
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ret = regulator_enable(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref enable failed\n");
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return ret;
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}
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ret = regulator_get_voltage(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
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goto err_regulator_disable;
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}
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priv->common.vref_mv = ret / 1000;
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dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
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priv->aclk = devm_clk_get(&pdev->dev, "adc");
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if (IS_ERR(priv->aclk)) {
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ret = PTR_ERR(priv->aclk);
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if (ret == -ENOENT) {
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priv->aclk = NULL;
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} else {
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if (ret != -ENOENT) {
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dev_err(&pdev->dev, "Can't get 'adc' clock\n");
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goto err_regulator_disable;
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}
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}
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if (priv->aclk) {
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ret = clk_prepare_enable(priv->aclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_regulator_disable;
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return ret;
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}
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priv->aclk = NULL;
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}
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priv->bclk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(priv->bclk)) {
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ret = PTR_ERR(priv->bclk);
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if (ret == -ENOENT) {
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priv->bclk = NULL;
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} else {
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if (ret != -ENOENT) {
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dev_err(&pdev->dev, "Can't get 'bus' clock\n");
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goto err_aclk_disable;
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return ret;
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}
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priv->bclk = NULL;
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}
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if (priv->bclk) {
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ret = clk_prepare_enable(priv->bclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_aclk_disable;
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}
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pm_runtime_get_noresume(dev);
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pm_runtime_set_active(dev);
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pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_enable(dev);
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ret = stm32_adc_core_hw_start(dev);
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if (ret)
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goto err_pm_stop;
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ret = regulator_get_voltage(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
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goto err_hw_stop;
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}
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priv->common.vref_mv = ret / 1000;
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dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
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ret = priv->cfg->clk_sel(pdev, priv);
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if (ret < 0)
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goto err_bclk_disable;
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goto err_hw_stop;
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ret = stm32_adc_irq_probe(pdev, priv);
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if (ret < 0)
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goto err_bclk_disable;
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platform_set_drvdata(pdev, &priv->common);
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goto err_hw_stop;
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ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
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if (ret < 0) {
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@ -478,21 +527,19 @@ static int stm32_adc_probe(struct platform_device *pdev)
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goto err_irq_remove;
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}
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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err_irq_remove:
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stm32_adc_irq_remove(pdev, priv);
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err_bclk_disable:
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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err_aclk_disable:
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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err_regulator_disable:
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regulator_disable(priv->vref);
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err_hw_stop:
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stm32_adc_core_hw_stop(dev);
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err_pm_stop:
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pm_runtime_disable(dev);
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pm_runtime_set_suspended(dev);
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pm_runtime_put_noidle(dev);
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return ret;
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}
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@ -502,17 +549,39 @@ static int stm32_adc_remove(struct platform_device *pdev)
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struct stm32_adc_common *common = platform_get_drvdata(pdev);
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struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
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pm_runtime_get_sync(&pdev->dev);
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of_platform_depopulate(&pdev->dev);
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stm32_adc_irq_remove(pdev, priv);
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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regulator_disable(priv->vref);
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stm32_adc_core_hw_stop(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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return 0;
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}
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#if defined(CONFIG_PM)
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static int stm32_adc_core_runtime_suspend(struct device *dev)
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{
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stm32_adc_core_hw_stop(dev);
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return 0;
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}
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static int stm32_adc_core_runtime_resume(struct device *dev)
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{
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return stm32_adc_core_hw_start(dev);
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}
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#endif
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static const struct dev_pm_ops stm32_adc_core_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
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stm32_adc_core_runtime_resume,
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NULL)
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};
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static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
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.regs = &stm32f4_adc_common_regs,
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.clk_sel = stm32f4_adc_clk_sel,
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@ -552,6 +621,7 @@ static struct platform_driver stm32_adc_driver = {
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.driver = {
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.name = "stm32-adc-core",
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.of_match_table = stm32_adc_of_match,
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.pm = &stm32_adc_core_pm_ops,
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},
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};
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module_platform_driver(stm32_adc_driver);
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@ -22,6 +22,7 @@
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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@ -148,6 +149,7 @@ enum stm32h7_adc_dmngt {
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#define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
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#define STM32_ADC_TIMEOUT_US 100000
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#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
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#define STM32_ADC_HW_STOP_DELAY_MS 100
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#define STM32_DMA_BUFFER_SIZE PAGE_SIZE
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@ -623,6 +625,47 @@ static void stm32_adc_set_res(struct stm32_adc *adc)
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stm32_adc_writel(adc, res->reg, val);
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}
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static int stm32_adc_hw_stop(struct device *dev)
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{
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struct stm32_adc *adc = dev_get_drvdata(dev);
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if (adc->cfg->unprepare)
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adc->cfg->unprepare(adc);
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if (adc->clk)
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clk_disable_unprepare(adc->clk);
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return 0;
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}
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static int stm32_adc_hw_start(struct device *dev)
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{
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struct stm32_adc *adc = dev_get_drvdata(dev);
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int ret;
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if (adc->clk) {
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ret = clk_prepare_enable(adc->clk);
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if (ret)
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return ret;
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}
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stm32_adc_set_res(adc);
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if (adc->cfg->prepare) {
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ret = adc->cfg->prepare(adc);
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if (ret)
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goto err_clk_dis;
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}
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return 0;
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err_clk_dis:
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if (adc->clk)
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clk_disable_unprepare(adc->clk);
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return ret;
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}
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/**
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* stm32f4_adc_start_conv() - Start conversions for regular channels.
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* @adc: stm32 adc instance
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@ -1171,6 +1214,7 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
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int *res)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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struct device *dev = indio_dev->dev.parent;
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const struct stm32_adc_regspec *regs = adc->cfg->regs;
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long timeout;
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u32 val;
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@ -1180,10 +1224,10 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
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adc->bufi = 0;
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if (adc->cfg->prepare) {
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ret = adc->cfg->prepare(adc);
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if (ret)
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return ret;
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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pm_runtime_put_noidle(dev);
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return ret;
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}
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/* Apply sampling time settings */
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@ -1221,8 +1265,8 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev,
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stm32_adc_conv_irq_disable(adc);
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if (adc->cfg->unprepare)
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adc->cfg->unprepare(adc);
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return ret;
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}
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@ -1330,15 +1374,22 @@ static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
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const unsigned long *scan_mask)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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struct device *dev = indio_dev->dev.parent;
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int ret;
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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pm_runtime_put_noidle(dev);
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return ret;
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}
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adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
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ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
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if (ret)
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return ret;
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return 0;
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return ret;
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}
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static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
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@ -1368,12 +1419,23 @@ static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
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unsigned *readval)
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{
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struct stm32_adc *adc = iio_priv(indio_dev);
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struct device *dev = indio_dev->dev.parent;
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int ret;
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
|
||||
pm_runtime_put_noidle(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!readval)
|
||||
stm32_adc_writel(adc, reg, writeval);
|
||||
else
|
||||
*readval = stm32_adc_readl(adc, reg);
|
||||
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1459,18 +1521,19 @@ static int stm32_adc_dma_start(struct iio_dev *indio_dev)
|
|||
static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
struct device *dev = indio_dev->dev.parent;
|
||||
int ret;
|
||||
|
||||
if (adc->cfg->prepare) {
|
||||
ret = adc->cfg->prepare(adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
|
||||
if (ret) {
|
||||
dev_err(&indio_dev->dev, "Can't set trigger\n");
|
||||
goto err_unprepare;
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
ret = stm32_adc_dma_start(indio_dev);
|
||||
|
|
@ -1498,9 +1561,9 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|||
dmaengine_terminate_all(adc->dma_chan);
|
||||
err_clr_trig:
|
||||
stm32_adc_set_trig(indio_dev, NULL);
|
||||
err_unprepare:
|
||||
if (adc->cfg->unprepare)
|
||||
adc->cfg->unprepare(adc);
|
||||
err_pm_put:
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1508,6 +1571,7 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
|
|||
static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct stm32_adc *adc = iio_priv(indio_dev);
|
||||
struct device *dev = indio_dev->dev.parent;
|
||||
int ret;
|
||||
|
||||
adc->cfg->stop_conv(adc);
|
||||
|
|
@ -1524,8 +1588,8 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
|
|||
if (stm32_adc_set_trig(indio_dev, NULL))
|
||||
dev_err(&indio_dev->dev, "Can't clear trigger\n");
|
||||
|
||||
if (adc->cfg->unprepare)
|
||||
adc->cfg->unprepare(adc);
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1864,26 +1928,17 @@ static int stm32_adc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
if (adc->clk) {
|
||||
ret = clk_prepare_enable(adc->clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "clk enable failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = stm32_adc_of_get_resolution(indio_dev);
|
||||
if (ret < 0)
|
||||
goto err_clk_disable;
|
||||
stm32_adc_set_res(adc);
|
||||
return ret;
|
||||
|
||||
ret = stm32_adc_chan_of_init(indio_dev);
|
||||
if (ret < 0)
|
||||
goto err_clk_disable;
|
||||
return ret;
|
||||
|
||||
ret = stm32_adc_dma_request(indio_dev);
|
||||
if (ret < 0)
|
||||
goto err_clk_disable;
|
||||
return ret;
|
||||
|
||||
ret = iio_triggered_buffer_setup(indio_dev,
|
||||
&iio_pollfunc_store_time,
|
||||
|
|
@ -1894,15 +1949,35 @@ static int stm32_adc_probe(struct platform_device *pdev)
|
|||
goto err_dma_disable;
|
||||
}
|
||||
|
||||
/* Get stm32-adc-core PM online */
|
||||
pm_runtime_get_noresume(dev);
|
||||
pm_runtime_set_active(dev);
|
||||
pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = stm32_adc_hw_start(dev);
|
||||
if (ret)
|
||||
goto err_buffer_cleanup;
|
||||
|
||||
ret = iio_device_register(indio_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "iio dev register failed\n");
|
||||
goto err_buffer_cleanup;
|
||||
goto err_hw_stop;
|
||||
}
|
||||
|
||||
pm_runtime_mark_last_busy(dev);
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_stop:
|
||||
stm32_adc_hw_stop(dev);
|
||||
|
||||
err_buffer_cleanup:
|
||||
pm_runtime_disable(dev);
|
||||
pm_runtime_set_suspended(dev);
|
||||
pm_runtime_put_noidle(dev);
|
||||
iio_triggered_buffer_cleanup(indio_dev);
|
||||
|
||||
err_dma_disable:
|
||||
|
|
@ -1912,9 +1987,6 @@ static int stm32_adc_probe(struct platform_device *pdev)
|
|||
adc->rx_buf, adc->rx_dma_buf);
|
||||
dma_release_channel(adc->dma_chan);
|
||||
}
|
||||
err_clk_disable:
|
||||
if (adc->clk)
|
||||
clk_disable_unprepare(adc->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1924,7 +1996,12 @@ static int stm32_adc_remove(struct platform_device *pdev)
|
|||
struct stm32_adc *adc = platform_get_drvdata(pdev);
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
iio_device_unregister(indio_dev);
|
||||
stm32_adc_hw_stop(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
pm_runtime_set_suspended(&pdev->dev);
|
||||
pm_runtime_put_noidle(&pdev->dev);
|
||||
iio_triggered_buffer_cleanup(indio_dev);
|
||||
if (adc->dma_chan) {
|
||||
dma_free_coherent(adc->dma_chan->device->dev,
|
||||
|
|
@ -1932,12 +2009,29 @@ static int stm32_adc_remove(struct platform_device *pdev)
|
|||
adc->rx_buf, adc->rx_dma_buf);
|
||||
dma_release_channel(adc->dma_chan);
|
||||
}
|
||||
if (adc->clk)
|
||||
clk_disable_unprepare(adc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
static int stm32_adc_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return stm32_adc_hw_stop(dev);
|
||||
}
|
||||
|
||||
static int stm32_adc_runtime_resume(struct device *dev)
|
||||
{
|
||||
return stm32_adc_hw_start(dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops stm32_adc_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static const struct stm32_adc_cfg stm32f4_adc_cfg = {
|
||||
.regs = &stm32f4_adc_regspec,
|
||||
.adc_info = &stm32f4_adc_info,
|
||||
|
|
@ -1985,6 +2079,7 @@ static struct platform_driver stm32_adc_driver = {
|
|||
.driver = {
|
||||
.name = "stm32-adc",
|
||||
.of_match_table = stm32_adc_of_match,
|
||||
.pm = &stm32_adc_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(stm32_adc_driver);
|
||||
|
|
|
|||
Loading…
Reference in New Issue