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pinctrl: tegra-xusb: Correct lane mux options 

The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
documentation implies that all functions (pcie, usb3 and sata) can be
muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
been confirmed that this is not the case and the mux'ing options much more
limited. Unfortunately, the public documentation has not been updated to
reflect this and so detail the actual mux'ing options here by function:

Function:		Lanes:
pcie1 x2:		pcie3, pcie4
pcie1 x4:		pcie1, pcie2, pcie3, pcie4
pcie2 x1 (option1):	pcie0
pcie2 x1 (option2):	pcie2
usb3 port 0:		pcie0
usb3 port 1 (option 1):	pcie1
usb3 port 1 (option 2):	sata0
sata:			sata0

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jon Hunter 2015-10-16 10:24:01 +01:00 committed by Linus Walleij
parent ee1a6ca43d
commit 9d4cc85d29
1 changed files with 0 additions and 9 deletions
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9
drivers/pinctrl/pinctrl-tegra-xusb.c
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@ -760,24 +760,15 @@ static const char * const tegra124_pcie_groups[] = {
"pcie-2",
"pcie-3",
"pcie-4",
"sata-0",
};
static const char * const tegra124_usb3_groups[] = {
"pcie-0",
"pcie-1",
"pcie-2",
"pcie-3",
"pcie-4",
"sata-0",
};
static const char * const tegra124_sata_groups[] = {
"pcie-0",
"pcie-1",
"pcie-2",
"pcie-3",
"pcie-4",
"sata-0",
};