spi: stm32: split transfer one setup function
Split stm32_spi_transfer_one_setup function into smaller chunks to be more generic for other stm32 SPI family drivers. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Gapinski
Mark Brown
parent
a9675337ad
commit
9d5fce166c
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@ -101,11 +101,18 @@
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#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
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#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
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/* SPI Communication mode */
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/* STM32H7 SPI Communication mode */
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#define STM32H7_SPI_FULL_DUPLEX 0
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#define STM32H7_SPI_SIMPLEX_TX 1
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#define STM32H7_SPI_SIMPLEX_RX 2
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#define STM32H7_SPI_HALF_DUPLEX 3
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/* SPI Communication type */
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#define SPI_FULL_DUPLEX 0
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#define SPI_SIMPLEX_TX 1
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#define SPI_SIMPLEX_RX 2
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#define SPI_HALF_DUPLEX 3
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#define SPI_3WIRE_TX 3
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#define SPI_3WIRE_RX 4
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#define SPI_1HZ_NS 1000000000
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@ -232,13 +239,16 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
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}
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/**
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* stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
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* stm32_spi_prepare_mbr - Determine baud rate divisor value
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* @spi: pointer to the spi controller data structure
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* @speed_hz: requested speed
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* @min_div: minimum baud rate divisor
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* @max_div: maximum baud rate divisor
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*
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* Return SPI_CFG1.MBR value in case of success or -EINVAL
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* Return baud rate divisor value in case of success or -EINVAL
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*/
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static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
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static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
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u32 min_div, u32 max_div)
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{
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u32 div, mbrdiv;
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@ -251,8 +261,7 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
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* no need to check it there.
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* However, we need to ensure the following calculations.
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*/
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if (div < STM32H7_SPI_MBR_DIV_MIN ||
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div > STM32H7_SPI_MBR_DIV_MAX)
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if ((div < min_div) || (div > max_div))
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return -EINVAL;
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/* Determine the first power of 2 greater than or equal to div */
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@ -802,7 +811,8 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
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}
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if (tx_dma_desc) {
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if (spi->cur_comm == SPI_SIMPLEX_TX) {
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if (spi->cur_comm == SPI_SIMPLEX_TX ||
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spi->cur_comm == SPI_3WIRE_TX) {
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tx_dma_desc->callback = stm32_spi_dma_cb;
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tx_dma_desc->callback_param = spi;
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}
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@ -847,6 +857,170 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
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return stm32_spi_transfer_one_irq(spi);
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}
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/**
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* stm32_spi_set_bpw - configure bits per word
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* @spi: pointer to the spi controller data structure
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*/
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static void stm32_spi_set_bpw(struct stm32_spi *spi)
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{
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u32 bpw, fthlv;
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u32 cfg1_clrb = 0, cfg1_setb = 0;
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bpw = spi->cur_bpw - 1;
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cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
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cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
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STM32H7_SPI_CFG1_DSIZE;
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spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
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fthlv = spi->cur_fthlv - 1;
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cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
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cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
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STM32H7_SPI_CFG1_FTHLV;
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writel_relaxed(
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(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
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~cfg1_clrb) | cfg1_setb,
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spi->base + STM32H7_SPI_CFG1);
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}
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/**
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* stm32_spi_set_mbr - Configure baud rate divisor in master mode
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* @spi: pointer to the spi controller data structure
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* @mbrdiv: baud rate divisor value
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*/
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static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
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{
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u32 cfg1_clrb = 0, cfg1_setb = 0;
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cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
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cfg1_setb |= ((u32)mbrdiv << STM32H7_SPI_CFG1_MBR_SHIFT) &
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STM32H7_SPI_CFG1_MBR;
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writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
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~cfg1_clrb) | cfg1_setb,
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spi->base + STM32H7_SPI_CFG1);
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}
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/**
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* stm32_spi_communication_type - return transfer communication type
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* @spi_dev: pointer to the spi device
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* transfer: pointer to spi transfer
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*/
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static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
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struct spi_transfer *transfer)
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{
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unsigned int type = SPI_FULL_DUPLEX;
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if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
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/*
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* SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
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* is forbidden and unvalidated by SPI subsystem so depending
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* on the valid buffer, we can determine the direction of the
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* transfer.
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*/
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if (!transfer->tx_buf)
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type = SPI_3WIRE_RX;
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else
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type = SPI_3WIRE_TX;
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} else {
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if (!transfer->tx_buf)
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type = SPI_SIMPLEX_RX;
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else if (!transfer->rx_buf)
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type = SPI_SIMPLEX_TX;
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}
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return type;
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}
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/**
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* stm32_spi_set_mode - configure communication mode
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* @spi: pointer to the spi controller data structure
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* @comm_type: type of communication to configure
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*/
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static int stm32_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
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{
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u32 mode;
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u32 cfg2_clrb = 0, cfg2_setb = 0;
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if (comm_type == SPI_3WIRE_RX) {
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mode = STM32H7_SPI_HALF_DUPLEX;
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stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
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} else if (comm_type == SPI_3WIRE_TX) {
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mode = STM32H7_SPI_HALF_DUPLEX;
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stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
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} else if (comm_type == SPI_SIMPLEX_RX) {
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mode = STM32H7_SPI_SIMPLEX_RX;
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} else if (comm_type == SPI_SIMPLEX_TX) {
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mode = STM32H7_SPI_SIMPLEX_TX;
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} else {
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mode = STM32H7_SPI_FULL_DUPLEX;
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}
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cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
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cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
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STM32H7_SPI_CFG2_COMM;
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writel_relaxed(
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(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
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~cfg2_clrb) | cfg2_setb,
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spi->base + STM32H7_SPI_CFG2);
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return 0;
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}
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/**
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* stm32_spi_data_idleness - configure minimum time delay inserted between two
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* consecutive data frames in master mode
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* @spi: pointer to the spi controller data structure
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* @len: transfer len
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*/
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static void stm32_spi_data_idleness(struct stm32_spi *spi, u32 len)
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{
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u32 cfg2_clrb = 0, cfg2_setb = 0;
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cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
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if ((len > 1) && (spi->cur_midi > 0)) {
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u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
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u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
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(u32)STM32H7_SPI_CFG2_MIDI >>
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STM32H7_SPI_CFG2_MIDI_SHIFT);
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dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
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sck_period_ns, midi, midi * sck_period_ns);
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cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
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STM32H7_SPI_CFG2_MIDI;
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}
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writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
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~cfg2_clrb) | cfg2_setb,
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spi->base + STM32H7_SPI_CFG2);
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}
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/**
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* stm32_spi_number_of_data - configure number of data at current transfer
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* @spi: pointer to the spi controller data structure
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* @len: transfer length
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*/
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static int stm32_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
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{
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u32 cr2_clrb = 0, cr2_setb = 0;
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if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
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STM32H7_SPI_CR2_TSIZE_SHIFT)) {
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cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
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cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
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writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
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~cr2_clrb) | cr2_setb,
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spi->base + STM32H7_SPI_CR2);
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} else {
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return -EMSGSIZE;
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}
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return 0;
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}
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/**
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* stm32_spi_transfer_one_setup - common setup to transfer a single
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* spi_transfer either using DMA or
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@ -857,99 +1031,43 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
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struct spi_transfer *transfer)
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{
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unsigned long flags;
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u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
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u32 mode, nb_words;
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int ret = 0;
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unsigned int comm_type;
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int nb_words, ret = 0;
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spin_lock_irqsave(&spi->lock, flags);
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if (spi->cur_bpw != transfer->bits_per_word) {
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u32 bpw, fthlv;
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spi->cur_bpw = transfer->bits_per_word;
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bpw = spi->cur_bpw - 1;
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cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
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cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
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STM32H7_SPI_CFG1_DSIZE;
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spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
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fthlv = spi->cur_fthlv - 1;
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cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
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cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
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STM32H7_SPI_CFG1_FTHLV;
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stm32_spi_set_bpw(spi);
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}
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if (spi->cur_speed != transfer->speed_hz) {
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int mbr;
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/* Update spi->cur_speed with real clock speed */
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mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
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mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
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STM32H7_SPI_MBR_DIV_MIN,
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STM32H7_SPI_MBR_DIV_MAX);
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if (mbr < 0) {
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ret = mbr;
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goto out;
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}
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transfer->speed_hz = spi->cur_speed;
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cfg1_clrb |= STM32H7_SPI_CFG1_MBR;
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cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) &
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STM32H7_SPI_CFG1_MBR;
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stm32_spi_set_mbr(spi, mbr);
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}
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if (cfg1_clrb || cfg1_setb)
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writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
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~cfg1_clrb) | cfg1_setb,
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spi->base + STM32H7_SPI_CFG1);
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comm_type = stm32_spi_communication_type(spi_dev, transfer);
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if (spi->cur_comm != comm_type) {
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stm32_spi_set_mode(spi, comm_type);
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mode = SPI_FULL_DUPLEX;
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if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
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/*
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* SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
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* is forbidden und unvalidated by SPI subsystem so depending
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* on the valid buffer, we can determine the direction of the
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* transfer.
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*/
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mode = SPI_HALF_DUPLEX;
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if (!transfer->tx_buf)
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stm32_spi_clr_bits(spi, STM32H7_SPI_CR1,
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STM32H7_SPI_CR1_HDDIR);
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else if (!transfer->rx_buf)
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stm32_spi_set_bits(spi, STM32H7_SPI_CR1,
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STM32H7_SPI_CR1_HDDIR);
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} else {
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if (!transfer->tx_buf)
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mode = SPI_SIMPLEX_RX;
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else if (!transfer->rx_buf)
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mode = SPI_SIMPLEX_TX;
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}
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if (spi->cur_comm != mode) {
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spi->cur_comm = mode;
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if (ret < 0)
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goto out;
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cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
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cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
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STM32H7_SPI_CFG2_COMM;
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spi->cur_comm = comm_type;
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}
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cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
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if ((transfer->len > 1) && (spi->cur_midi > 0)) {
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u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
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u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
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(u32)STM32H7_SPI_CFG2_MIDI >>
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STM32H7_SPI_CFG2_MIDI_SHIFT);
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dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
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sck_period_ns, midi, midi * sck_period_ns);
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cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
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STM32H7_SPI_CFG2_MIDI;
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}
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if (cfg2_clrb || cfg2_setb)
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writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
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~cfg2_clrb) | cfg2_setb,
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spi->base + STM32H7_SPI_CFG2);
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stm32_spi_data_idleness(spi, transfer->len);
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if (spi->cur_bpw <= 8)
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nb_words = transfer->len;
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@ -957,14 +1075,10 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
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nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
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else
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nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
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nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT;
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if (nb_words <= STM32H7_SPI_CR2_TSIZE) {
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writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2);
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} else {
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ret = -EMSGSIZE;
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ret = stm32_spi_number_of_data(spi, nb_words);
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if (ret < 0)
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goto out;
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}
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spi->cur_xferlen = transfer->len;
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