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clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data 

1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
   add a variable to indicate this change and
   backward-compatible.

2. fmin: The PLL frequency lower-bound is vary from 1GHz to
   1.5GHz, add a variable to indicate platform-dependent.

Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Owen Chen 2019-03-05 13:05:40 +08:00 committed by Stephen Boyd
parent a3ae549917
commit 9d7e1a82b7
2 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/mediatek/clk-mtk.h
View File

@ -227,8 +227,10 @@ struct mtk_pll_data {
unsigned int flags;
const struct clk_ops *ops;
u32 rst_bar_mask;
unsigned long fmin;
unsigned long fmax;
int pcwbits;
int pcwibits;
uint32_t pcw_reg;
int pcw_shift;
const struct mtk_pll_div_table *div_table;

15
drivers/clk/mediatek/clk-pll.c
View File

@ -32,6 +32,8 @@
#define AUDPLL_TUNER_EN BIT(31)
#define POSTDIV_MASK 0x7
/* default 7 bits integer, can be overridden with pcwibits. */
#define INTEGER_BITS 7
/*
@ -68,12 +70,15 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
int pcwbits = pll->data->pcwbits;
int pcwfbits;
int pcwfbits = 0;
int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
if (pcwbits > ibits)
pcwfbits = pcwbits - ibits;
vco = (u64)fin * pcw;
@ -170,9 +175,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
{
unsigned long fmin = 1000 * MHZ;
unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
const struct mtk_pll_div_table *div_table = pll->data->div_table;
u64 _pcw;
int ibits;
u32 val;
if (freq > pll->data->fmax)
@ -196,7 +202,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
}
/* _pcw = freq * postdiv / fin * 2^pcwfbits */
_pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
do_div(_pcw, fin);
*pcw = (u32)_pcw;