arm64: Refactor sysinstr exception handling
Right now we trap some of the user space data cache operations based on a few Errata (ARM 819472, 826319, 827319 and 824069). We need to trap userspace access to CTR_EL0, if we detect mismatched cache line size. Since both these traps share the EC, refactor the handler a little bit to make it a bit more reader friendly. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -78,6 +78,23 @@
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#define ESR_ELx_IL (UL(1) << 25)
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#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
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/* ISS field definitions shared by different classes */
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#define ESR_ELx_WNR (UL(1) << 6)
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/* Shared ISS field definitions for Data/Instruction aborts */
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#define ESR_ELx_EA (UL(1) << 9)
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#define ESR_ELx_S1PTW (UL(1) << 7)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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/* ISS field definitions for Data Aborts */
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#define ESR_ELx_ISV (UL(1) << 24)
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#define ESR_ELx_SAS_SHIFT (22)
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#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
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@ -86,16 +103,9 @@
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#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
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#define ESR_ELx_SF (UL(1) << 15)
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#define ESR_ELx_AR (UL(1) << 14)
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#define ESR_ELx_EA (UL(1) << 9)
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#define ESR_ELx_CM (UL(1) << 8)
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#define ESR_ELx_S1PTW (UL(1) << 7)
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#define ESR_ELx_WNR (UL(1) << 6)
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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/* ISS field definitions for exceptions taken in to Hyp */
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#define ESR_ELx_CV (UL(1) << 24)
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#define ESR_ELx_COND_SHIFT (20)
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#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
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@ -109,6 +119,54 @@
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((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \
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((imm) & 0xffff))
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/* ISS field definitions for System instruction traps */
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#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
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#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
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#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
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#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
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#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
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#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
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#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
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#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
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#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
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#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
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#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
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#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
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#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_CRM_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
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/*
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* User space cache operations have the following sysreg encoding
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* in System instructions.
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* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 14 }, WRITE (L=0)
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*/
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#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
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#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
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(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
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ESR_ELx_SYS64_ISS_DIR_WRITE)
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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@ -447,36 +447,29 @@ void cpu_enable_cache_maint_trap(void *__unused)
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: "=r" (res) \
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: "r" (address), "i" (-EFAULT) )
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asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
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static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
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{
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unsigned long address;
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int ret;
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
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int ret = 0;
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/* if this is a write with: Op0=1, Op2=1, Op1=3, CRn=7 */
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if ((esr & 0x01fffc01) == 0x0012dc00) {
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int rt = (esr >> 5) & 0x1f;
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int crm = (esr >> 1) & 0x0f;
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address = (rt == 31) ? 0 : regs->regs[rt];
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address = (rt == 31) ? 0 : regs->regs[rt];
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switch (crm) {
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case 11: /* DC CVAU, gets promoted */
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__user_cache_maint("dc civac", address, ret);
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break;
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case 10: /* DC CVAC, gets promoted */
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__user_cache_maint("dc civac", address, ret);
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break;
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case 14: /* DC CIVAC */
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__user_cache_maint("dc civac", address, ret);
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break;
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case 5: /* IC IVAU */
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__user_cache_maint("ic ivau", address, ret);
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break;
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default:
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force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
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return;
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}
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} else {
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switch (crm) {
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
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__user_cache_maint("dc civac", address, ret);
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break;
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
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__user_cache_maint("dc civac", address, ret);
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break;
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case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
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__user_cache_maint("dc civac", address, ret);
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break;
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case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
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__user_cache_maint("ic ivau", address, ret);
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break;
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default:
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force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
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return;
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}
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@ -487,6 +480,34 @@ asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
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regs->pc += 4;
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}
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struct sys64_hook {
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unsigned int esr_mask;
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unsigned int esr_val;
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void (*handler)(unsigned int esr, struct pt_regs *regs);
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};
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static struct sys64_hook sys64_hooks[] = {
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{
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.esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
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.esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
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.handler = user_cache_maint_handler,
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},
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{},
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};
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asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
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{
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struct sys64_hook *hook;
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for (hook = sys64_hooks; hook->handler; hook++)
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if ((hook->esr_mask & esr) == hook->esr_val) {
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hook->handler(esr, regs);
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return;
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}
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force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
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}
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long compat_arm_syscall(struct pt_regs *regs);
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asmlinkage long do_ni_syscall(struct pt_regs *regs)
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