Second Round of Renesas ARM Based SoC DT Updates for v4.10
Enhancements:
* Add device nodes for PRR
* Add r8a7745 SoC and sk-rzg1e board
* Add r8a7743 SoC and sk-rzg1m board
* Enable SDR-104 and I2C demuxer on alt, koelsch and lager boards
Corrections:
* Use SYSC "always-on" PM Domain for sound on r8a7794 SoC
* Correct hsusb parent clock on r8a7794 SoC
* Correct PFC names for DU on alt board
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Merge tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.10" from Simon Horman:
Enhancements:
* Add device nodes for PRR
* Add r8a7745 SoC and sk-rzg1e board
* Add r8a7743 SoC and sk-rzg1m board
* Enable SDR-104 and I2C demuxer on alt, koelsch and lager boards
Corrections:
* Use SYSC "always-on" PM Domain for sound on r8a7794 SoC
* Correct hsusb parent clock on r8a7794 SoC
* Correct PFC names for DU on alt board
* tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (33 commits)
ARM: dts: r8a7794: Add device node for PRR
ARM: dts: r8a7793: Add device node for PRR
ARM: dts: r8a7792: Add device node for PRR
ARM: dts: r8a7791: Add device node for PRR
ARM: dts: r8a7790: Add device node for PRR
ARM: dts: r8a7779: Add device node for PRR
ARM: dts: r8a73a4: Add device node for PRR
ARM: dts: sk-rzg1e: add Ether support
ARM: dts: sk-rzg1e: initial device tree
ARM: dts: r8a7745: add IRQC support
ARM: dts: r8a7745: add Ether support
ARM: dts: r8a7745: add [H]SCIF{|A|B} support
ARM: dts: r8a7745: add SYS-DMAC support
ARM: dts: r8a7745: initial SoC device tree
ARM: dts: sk-rzg1m: add Ether support
ARM: dts: sk-rzg1m: initial device tree
ARM: dts: r8a7743: add IRQC support
ARM: dts: r8a7743: add Ether support
ARM: dts: r8a7743: add [H]SCIF{A|B} support
ARM: dts: r8a7743: add SYS-DMAC support
...
This commit is contained in:
Arnd Bergmann
commit
9de194ff11
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@ -694,6 +694,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
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r7s72100-rskrza1.dtb \
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r7s72100-rskrza1.dtb \
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r8a73a4-ape6evm.dtb \
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r8a73a4-ape6evm.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7743-sk-rzg1m.dtb \
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r8a7745-sk-rzg1e.dtb \
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r8a7778-bockw.dtb \
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r8a7778-bockw.dtb \
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r8a7779-marzen.dtb \
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r8a7779-marzen.dtb \
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r8a7790-lager.dtb \
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r8a7790-lager.dtb \
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@ -751,6 +751,11 @@ R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
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};
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};
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};
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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sysc: system-controller@e6180000 {
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sysc: system-controller@e6180000 {
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compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
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compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
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reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
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reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
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@ -0,0 +1,57 @@
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/*
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* Device Tree Source for the SK-RZG1M board
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*
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* Copyright (C) 2016 Cogent Embedded, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7743.dtsi"
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/ {
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model = "SK-RZG1M";
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compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
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aliases {
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serial0 = &scif0;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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memory@200000000 {
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device_type = "memory";
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reg = <2 0x00000000 0 0x40000000>;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&scif0 {
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status = "okay";
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};
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ðer {
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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};
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};
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@ -0,0 +1,476 @@
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/*
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* Device Tree Source for the r8a7743 SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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|
* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
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#include <dt-bindings/power/r8a7743-sysc.h>
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/ {
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compatible = "renesas,r8a7743";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
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power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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};
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L2_CA15: cache-controller@0 {
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compatible = "cache";
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reg = <0>;
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7743_PD_CA15_SCU>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7743", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7743-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7743-sysc";
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reg = <0 0xe6180000 0 0x200>;
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#power-domain-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7743-rst";
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reg = <0 0xe6160000 0 0x100>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7743",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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|
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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|
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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||||||
|
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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||||||
|
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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|
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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|
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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|
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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|
interrupt-names = "error",
|
||||||
|
"ch0", "ch1", "ch2", "ch3",
|
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|
"ch4", "ch5", "ch6", "ch7",
|
||||||
|
"ch8", "ch9", "ch10", "ch11",
|
||||||
|
"ch12", "ch13", "ch14";
|
||||||
|
clocks = <&cpg CPG_MOD 219>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
dma-channels = <15>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dmac1: dma-controller@e6720000 {
|
||||||
|
compatible = "renesas,dmac-r8a7743",
|
||||||
|
"renesas,rcar-dmac";
|
||||||
|
reg = <0 0xe6720000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "error",
|
||||||
|
"ch0", "ch1", "ch2", "ch3",
|
||||||
|
"ch4", "ch5", "ch6", "ch7",
|
||||||
|
"ch8", "ch9", "ch10", "ch11",
|
||||||
|
"ch12", "ch13", "ch14";
|
||||||
|
clocks = <&cpg CPG_MOD 218>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
dma-channels = <15>;
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa0: serial@e6c40000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c40000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 204>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x21>, <&dmac0 0x22>,
|
||||||
|
<&dmac1 0x21>, <&dmac1 0x22>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa1: serial@e6c50000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c50000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 203>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x25>, <&dmac0 0x26>,
|
||||||
|
<&dmac1 0x25>, <&dmac1 0x26>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa2: serial@e6c60000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c60000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 202>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x27>, <&dmac0 0x28>,
|
||||||
|
<&dmac1 0x27>, <&dmac1 0x28>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa3: serial@e6c70000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c70000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1106>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
|
||||||
|
<&dmac1 0x1b>, <&dmac1 0x1c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa4: serial@e6c78000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c78000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1107>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
|
||||||
|
<&dmac1 0x1f>, <&dmac1 0x20>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa5: serial@e6c80000 {
|
||||||
|
compatible = "renesas,scifa-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c80000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1108>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x23>, <&dmac0 0x24>,
|
||||||
|
<&dmac1 0x23>, <&dmac1 0x24>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb0: serial@e6c20000 {
|
||||||
|
compatible = "renesas,scifb-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6c20000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 206>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
|
||||||
|
<&dmac1 0x3d>, <&dmac1 0x3e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb1: serial@e6c30000 {
|
||||||
|
compatible = "renesas,scifb-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6c30000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 207>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
|
||||||
|
<&dmac1 0x19>, <&dmac1 0x1a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb2: serial@e6ce0000 {
|
||||||
|
compatible = "renesas,scifb-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6ce0000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 216>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
|
||||||
|
<&dmac1 0x1d>, <&dmac1 0x1e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif0: serial@e6e60000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e60000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 721>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
||||||
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif1: serial@e6e68000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e68000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 720>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
||||||
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif2: serial@e6e58000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e58000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 719>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
||||||
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif3: serial@e6ea8000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ea8000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 718>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
||||||
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif4: serial@e6ee0000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ee0000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 715>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
|
||||||
|
<&dmac1 0xfb>, <&dmac1 0xfc>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif5: serial@e6ee8000 {
|
||||||
|
compatible = "renesas,scif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ee8000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 714>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
|
||||||
|
<&dmac1 0xfd>, <&dmac1 0xfe>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif0: serial@e62c0000 {
|
||||||
|
compatible = "renesas,hscif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62c0000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 717>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
||||||
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif1: serial@e62c8000 {
|
||||||
|
compatible = "renesas,hscif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62c8000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 716>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
||||||
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif2: serial@e62d0000 {
|
||||||
|
compatible = "renesas,hscif-r8a7743",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62d0000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 713>,
|
||||||
|
<&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
|
||||||
|
<&dmac1 0x3b>, <&dmac1 0x3c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
ether: ethernet@ee700000 {
|
||||||
|
compatible = "renesas,ether-r8a7743";
|
||||||
|
reg = <0 0xee700000 0 0x400>;
|
||||||
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 813>;
|
||||||
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
||||||
|
phy-mode = "rmii";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External root clock */
|
||||||
|
extal_clk: extal {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
/* This value must be overridden by the board. */
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External USB clock - can be overridden by the board */
|
||||||
|
usb_extal_clk: usb_extal {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External SCIF clock */
|
||||||
|
scif_clk: scif {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
/* This value must be overridden by the board. */
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for the SK-RZG1E board
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||||
|
*
|
||||||
|
* This file is licensed under the terms of the GNU General Public License
|
||||||
|
* version 2. This program is licensed "as is" without any warranty of any
|
||||||
|
* kind, whether express or implied.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "r8a7745.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "SK-RZG1E";
|
||||||
|
compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &scif2;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@40000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0 0x40000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&extal_clk {
|
||||||
|
clock-frequency = <20000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&scif2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
ðer {
|
||||||
|
phy-handle = <&phy1>;
|
||||||
|
renesas,ether-link-active-low;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
phy1: ethernet-phy@1 {
|
||||||
|
reg = <1>;
|
||||||
|
interrupt-parent = <&irqc>;
|
||||||
|
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
micrel,led-mode = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,476 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for the r8a7745 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||||
|
*
|
||||||
|
* This file is licensed under the terms of the GNU General Public License
|
||||||
|
* version 2. This program is licensed "as is" without any warranty of any
|
||||||
|
* kind, whether express or implied.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
|
||||||
|
#include <dt-bindings/power/r8a7745-sysc.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "renesas,r8a7745";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu0: cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a7";
|
||||||
|
reg = <0>;
|
||||||
|
clock-frequency = <1000000000>;
|
||||||
|
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
|
||||||
|
power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
|
||||||
|
next-level-cache = <&L2_CA7>;
|
||||||
|
};
|
||||||
|
|
||||||
|
L2_CA7: cache-controller@0 {
|
||||||
|
compatible = "cache";
|
||||||
|
reg = <0>;
|
||||||
|
cache-unified;
|
||||||
|
cache-level = <2>;
|
||||||
|
power-domains = <&sysc R8A7745_PD_CA7_SCU>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
gic: interrupt-controller@f1001000 {
|
||||||
|
compatible = "arm,gic-400";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0 0xf1001000 0 0x1000>,
|
||||||
|
<0 0xf1002000 0 0x1000>,
|
||||||
|
<0 0xf1004000 0 0x2000>,
|
||||||
|
<0 0xf1006000 0 0x2000>;
|
||||||
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||||
|
IRQ_TYPE_LEVEL_HIGH)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
irqc: interrupt-controller@e61c0000 {
|
||||||
|
compatible = "renesas,irqc-r8a7745", "renesas,irqc";
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0 0xe61c0000 0 0x200>;
|
||||||
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 407>;
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv7-timer";
|
||||||
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||||
|
IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||||
|
IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
|
||||||
|
IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
|
||||||
|
IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpg: clock-controller@e6150000 {
|
||||||
|
compatible = "renesas,r8a7745-cpg-mssr";
|
||||||
|
reg = <0 0xe6150000 0 0x1000>;
|
||||||
|
clocks = <&extal_clk>, <&usb_extal_clk>;
|
||||||
|
clock-names = "extal", "usb_extal";
|
||||||
|
#clock-cells = <2>;
|
||||||
|
#power-domain-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysc: system-controller@e6180000 {
|
||||||
|
compatible = "renesas,r8a7745-sysc";
|
||||||
|
reg = <0 0xe6180000 0 0x200>;
|
||||||
|
#power-domain-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rst: reset-controller@e6160000 {
|
||||||
|
compatible = "renesas,r8a7745-rst";
|
||||||
|
reg = <0 0xe6160000 0 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dmac0: dma-controller@e6700000 {
|
||||||
|
compatible = "renesas,dmac-r8a7745",
|
||||||
|
"renesas,rcar-dmac";
|
||||||
|
reg = <0 0xe6700000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "error",
|
||||||
|
"ch0", "ch1", "ch2", "ch3",
|
||||||
|
"ch4", "ch5", "ch6", "ch7",
|
||||||
|
"ch8", "ch9", "ch10", "ch11",
|
||||||
|
"ch12", "ch13", "ch14";
|
||||||
|
clocks = <&cpg CPG_MOD 219>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
dma-channels = <15>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dmac1: dma-controller@e6720000 {
|
||||||
|
compatible = "renesas,dmac-r8a7745",
|
||||||
|
"renesas,rcar-dmac";
|
||||||
|
reg = <0 0xe6720000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||||
|
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "error",
|
||||||
|
"ch0", "ch1", "ch2", "ch3",
|
||||||
|
"ch4", "ch5", "ch6", "ch7",
|
||||||
|
"ch8", "ch9", "ch10", "ch11",
|
||||||
|
"ch12", "ch13", "ch14";
|
||||||
|
clocks = <&cpg CPG_MOD 218>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
#dma-cells = <1>;
|
||||||
|
dma-channels = <15>;
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa0: serial@e6c40000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c40000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 204>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x21>, <&dmac0 0x22>,
|
||||||
|
<&dmac1 0x21>, <&dmac1 0x22>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa1: serial@e6c50000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c50000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 203>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x25>, <&dmac0 0x26>,
|
||||||
|
<&dmac1 0x25>, <&dmac1 0x26>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa2: serial@e6c60000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c60000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 202>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x27>, <&dmac0 0x28>,
|
||||||
|
<&dmac1 0x27>, <&dmac1 0x28>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa3: serial@e6c70000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c70000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1106>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
|
||||||
|
<&dmac1 0x1b>, <&dmac1 0x1c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa4: serial@e6c78000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c78000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1107>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
|
||||||
|
<&dmac1 0x1f>, <&dmac1 0x20>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifa5: serial@e6c80000 {
|
||||||
|
compatible = "renesas,scifa-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||||
|
reg = <0 0xe6c80000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 1108>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x23>, <&dmac0 0x24>,
|
||||||
|
<&dmac1 0x23>, <&dmac1 0x24>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb0: serial@e6c20000 {
|
||||||
|
compatible = "renesas,scifb-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6c20000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 206>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
|
||||||
|
<&dmac1 0x3d>, <&dmac1 0x3e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb1: serial@e6c30000 {
|
||||||
|
compatible = "renesas,scifb-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6c30000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 207>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
|
||||||
|
<&dmac1 0x19>, <&dmac1 0x1a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scifb2: serial@e6ce0000 {
|
||||||
|
compatible = "renesas,scifb-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
||||||
|
reg = <0 0xe6ce0000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 216>;
|
||||||
|
clock-names = "fck";
|
||||||
|
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
|
||||||
|
<&dmac1 0x1d>, <&dmac1 0x1e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif0: serial@e6e60000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e60000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 721>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
||||||
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif1: serial@e6e68000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e68000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 720>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
||||||
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif2: serial@e6e58000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6e58000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 719>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
||||||
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif3: serial@e6ea8000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ea8000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 718>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
||||||
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif4: serial@e6ee0000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ee0000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 715>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
|
||||||
|
<&dmac1 0xfb>, <&dmac1 0xfc>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
scif5: serial@e6ee8000 {
|
||||||
|
compatible = "renesas,scif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||||
|
reg = <0 0xe6ee8000 0 0x40>;
|
||||||
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 714>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
|
||||||
|
<&dmac1 0xfd>, <&dmac1 0xfe>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif0: serial@e62c0000 {
|
||||||
|
compatible = "renesas,hscif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62c0000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 717>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
||||||
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif1: serial@e62c8000 {
|
||||||
|
compatible = "renesas,hscif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62c8000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 716>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
||||||
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
hscif2: serial@e62d0000 {
|
||||||
|
compatible = "renesas,hscif-r8a7745",
|
||||||
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||||
|
reg = <0 0xe62d0000 0 0x60>;
|
||||||
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 713>,
|
||||||
|
<&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
|
||||||
|
clock-names = "fck", "brg_int", "scif_clk";
|
||||||
|
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
|
||||||
|
<&dmac1 0x3b>, <&dmac1 0x3c>;
|
||||||
|
dma-names = "tx", "rx", "tx", "rx";
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
ether: ethernet@ee700000 {
|
||||||
|
compatible = "renesas,ether-r8a7745";
|
||||||
|
reg = <0 0xee700000 0 0x400>;
|
||||||
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cpg CPG_MOD 813>;
|
||||||
|
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
|
||||||
|
phy-mode = "rmii";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External root clock */
|
||||||
|
extal_clk: extal {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
/* This value must be overridden by the board. */
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External USB clock - can be overridden by the board */
|
||||||
|
usb_extal_clk: usb_extal {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* External SCIF clock */
|
||||||
|
scif_clk: scif {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
/* This value must be overridden by the board. */
|
||||||
|
clock-frequency = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -590,6 +590,11 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0xff000044 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@ffd85000 {
|
sysc: system-controller@ffd85000 {
|
||||||
compatible = "renesas,r8a7779-sysc";
|
compatible = "renesas,r8a7779-sysc";
|
||||||
reg = <0xffd85000 0x0200>;
|
reg = <0xffd85000 0x0200>;
|
||||||
|
|
|
||||||
|
|
@ -50,7 +50,9 @@ / {
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &scif0;
|
serial0 = &scif0;
|
||||||
serial1 = &scifa1;
|
serial1 = &scifa1;
|
||||||
i2c8 = "i2cexio";
|
i2c8 = &gpioi2c1;
|
||||||
|
i2c10 = &i2cexio0;
|
||||||
|
i2c11 = &i2cexio1;
|
||||||
};
|
};
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
|
|
@ -265,6 +267,17 @@ x13_clk: x13-clock {
|
||||||
clock-frequency = <148500000>;
|
clock-frequency = <148500000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpioi2c1: i2c-8 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "i2c-gpio";
|
||||||
|
status = "disabled";
|
||||||
|
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
|
||||||
|
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
|
||||||
|
>;
|
||||||
|
i2c-gpio,delay-us = <5>;
|
||||||
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
|
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
|
||||||
* We use the I2C demuxer, so the desired IP core can be selected at runtime
|
* We use the I2C demuxer, so the desired IP core can be selected at runtime
|
||||||
|
|
@ -273,11 +286,26 @@ x13_clk: x13-clock {
|
||||||
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
|
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
|
||||||
* instantiate the slave device at runtime according to the documentation.
|
* instantiate the slave device at runtime according to the documentation.
|
||||||
* You can then communicate with the slave via IIC3.
|
* You can then communicate with the slave via IIC3.
|
||||||
|
*
|
||||||
|
* IIC0/I2C0 does not appear to support fallback to GPIO.
|
||||||
*/
|
*/
|
||||||
i2cexio: i2c-8 {
|
i2cexio0: i2c-10 {
|
||||||
compatible = "i2c-demux-pinctrl";
|
compatible = "i2c-demux-pinctrl";
|
||||||
i2c-parent = <&iic0>, <&i2c0>;
|
i2c-parent = <&iic0>, <&i2c0>;
|
||||||
i2c-bus-name = "i2c-exio";
|
i2c-bus-name = "i2c-exio0";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
|
||||||
|
* This is similar to the arangement described for i2cexio0 (above)
|
||||||
|
* with a fallback to GPIO also provided.
|
||||||
|
*/
|
||||||
|
i2cexio1: i2c-11 {
|
||||||
|
compatible = "i2c-demux-pinctrl";
|
||||||
|
i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
|
||||||
|
i2c-bus-name = "i2c-exio1";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
};
|
};
|
||||||
|
|
@ -403,6 +431,11 @@ iic0_pins: iic0 {
|
||||||
function = "iic0";
|
function = "iic0";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c1_pins: i2c1 {
|
||||||
|
groups = "i2c1";
|
||||||
|
function = "i2c1";
|
||||||
|
};
|
||||||
|
|
||||||
iic1_pins: iic1 {
|
iic1_pins: iic1 {
|
||||||
groups = "iic1";
|
groups = "iic1";
|
||||||
function = "iic1";
|
function = "iic1";
|
||||||
|
|
@ -575,6 +608,7 @@ &sdhi0 {
|
||||||
vqmmc-supply = <&vccq_sdhi0>;
|
vqmmc-supply = <&vccq_sdhi0>;
|
||||||
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||||
sd-uhs-sdr50;
|
sd-uhs-sdr50;
|
||||||
|
sd-uhs-sdr104;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -596,18 +630,22 @@ &cpu0 {
|
||||||
|
|
||||||
&i2c0 {
|
&i2c0 {
|
||||||
pinctrl-0 = <&i2c0_pins>;
|
pinctrl-0 = <&i2c0_pins>;
|
||||||
pinctrl-names = "i2c-exio";
|
pinctrl-names = "i2c-exio0";
|
||||||
};
|
};
|
||||||
|
|
||||||
&iic0 {
|
&iic0 {
|
||||||
pinctrl-0 = <&iic0_pins>;
|
pinctrl-0 = <&iic0_pins>;
|
||||||
pinctrl-names = "i2c-exio";
|
pinctrl-names = "i2c-exio0";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
pinctrl-0 = <&i2c1_pins>;
|
||||||
|
pinctrl-names = "i2c-exio1";
|
||||||
};
|
};
|
||||||
|
|
||||||
&iic1 {
|
&iic1 {
|
||||||
status = "okay";
|
|
||||||
pinctrl-0 = <&iic1_pins>;
|
pinctrl-0 = <&iic1_pins>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "i2c-exio1";
|
||||||
};
|
};
|
||||||
|
|
||||||
&iic2 {
|
&iic2 {
|
||||||
|
|
|
||||||
|
|
@ -1471,6 +1471,11 @@ R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_S
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0 0xff000044 0 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@e6180000 {
|
sysc: system-controller@e6180000 {
|
||||||
compatible = "renesas,r8a7790-sysc";
|
compatible = "renesas,r8a7790-sysc";
|
||||||
reg = <0 0xe6180000 0 0x0200>;
|
reg = <0 0xe6180000 0 0x0200>;
|
||||||
|
|
|
||||||
|
|
@ -50,6 +50,8 @@ / {
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &scif0;
|
serial0 = &scif0;
|
||||||
serial1 = &scif1;
|
serial1 = &scif1;
|
||||||
|
i2c9 = &gpioi2c1;
|
||||||
|
i2c12 = &i2cexio1;
|
||||||
};
|
};
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
|
|
@ -298,6 +300,29 @@ x13_clk: x13-clock {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <148500000>;
|
clock-frequency = <148500000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpioi2c1: i2c-9 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "i2c-gpio";
|
||||||
|
status = "disabled";
|
||||||
|
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
|
||||||
|
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
|
||||||
|
>;
|
||||||
|
i2c-gpio,delay-us = <5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
|
||||||
|
* A fallback to GPIO is provided.
|
||||||
|
*/
|
||||||
|
i2cexio1: i2c-12 {
|
||||||
|
compatible = "i2c-demux-pinctrl";
|
||||||
|
i2c-parent = <&i2c1>, <&gpioi2c1>;
|
||||||
|
i2c-bus-name = "i2c-exio1";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&du {
|
&du {
|
||||||
|
|
@ -333,6 +358,11 @@ &pfc {
|
||||||
pinctrl-0 = <&scif_clk_pins>;
|
pinctrl-0 = <&scif_clk_pins>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
||||||
|
i2c1_pins: i2c1 {
|
||||||
|
groups = "i2c1";
|
||||||
|
function = "i2c1";
|
||||||
|
};
|
||||||
|
|
||||||
i2c2_pins: i2c2 {
|
i2c2_pins: i2c2 {
|
||||||
groups = "i2c2";
|
groups = "i2c2";
|
||||||
function = "i2c2";
|
function = "i2c2";
|
||||||
|
|
@ -499,6 +529,7 @@ &sdhi0 {
|
||||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||||
sd-uhs-sdr50;
|
sd-uhs-sdr50;
|
||||||
|
sd-uhs-sdr104;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -581,6 +612,11 @@ pmic: pmic@0 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
pinctrl-0 = <&i2c1_pins>;
|
||||||
|
pinctrl-names = "i2c-exio1";
|
||||||
|
};
|
||||||
|
|
||||||
&i2c2 {
|
&i2c2 {
|
||||||
pinctrl-0 = <&i2c2_pins>;
|
pinctrl-0 = <&i2c2_pins>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
|
||||||
|
|
@ -1485,6 +1485,11 @@ R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0 0xff000044 0 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@e6180000 {
|
sysc: system-controller@e6180000 {
|
||||||
compatible = "renesas,r8a7791-sysc";
|
compatible = "renesas,r8a7791-sysc";
|
||||||
reg = <0 0xe6180000 0 0x0200>;
|
reg = <0 0xe6180000 0 0x0200>;
|
||||||
|
|
|
||||||
|
|
@ -120,6 +120,11 @@ IRQ_TYPE_LEVEL_LOW)>,
|
||||||
IRQ_TYPE_LEVEL_LOW)>;
|
IRQ_TYPE_LEVEL_LOW)>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0 0xff000044 0 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@e6180000 {
|
sysc: system-controller@e6180000 {
|
||||||
compatible = "renesas,r8a7792-sysc";
|
compatible = "renesas,r8a7792-sysc";
|
||||||
reg = <0 0xe6180000 0 0x0200>;
|
reg = <0 0xe6180000 0 0x0200>;
|
||||||
|
|
|
||||||
|
|
@ -1306,6 +1306,11 @@ R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0 0xff000044 0 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@e6180000 {
|
sysc: system-controller@e6180000 {
|
||||||
compatible = "renesas,r8a7793-sysc";
|
compatible = "renesas,r8a7793-sysc";
|
||||||
reg = <0 0xe6180000 0 0x0200>;
|
reg = <0 0xe6180000 0 0x0200>;
|
||||||
|
|
|
||||||
|
|
@ -18,6 +18,8 @@ / {
|
||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &scif2;
|
serial0 = &scif2;
|
||||||
|
i2c10 = &gpioi2c4;
|
||||||
|
i2c12 = &i2cexio4;
|
||||||
};
|
};
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
|
|
@ -135,6 +137,29 @@ x13_clk: x13-clock {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <148500000>;
|
clock-frequency = <148500000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpioi2c4: i2c-10 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "i2c-gpio";
|
||||||
|
status = "disabled";
|
||||||
|
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
|
||||||
|
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
|
||||||
|
>;
|
||||||
|
i2c-gpio,delay-us = <5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
|
||||||
|
* A fallback to GPIO is provided.
|
||||||
|
*/
|
||||||
|
i2cexio4: i2c-14 {
|
||||||
|
compatible = "i2c-demux-pinctrl";
|
||||||
|
i2c-parent = <&i2c4>, <&gpioi2c4>;
|
||||||
|
i2c-bus-name = "i2c-exio4";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&du {
|
&du {
|
||||||
|
|
@ -165,8 +190,8 @@ &pfc {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
||||||
du_pins: du {
|
du_pins: du {
|
||||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
|
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
|
||||||
function = "du";
|
function = "du1";
|
||||||
};
|
};
|
||||||
|
|
||||||
scif2_pins: scif2 {
|
scif2_pins: scif2 {
|
||||||
|
|
@ -194,6 +219,11 @@ i2c1_pins: i2c1 {
|
||||||
function = "i2c1";
|
function = "i2c1";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c4_pins: i2c4 {
|
||||||
|
groups = "i2c4";
|
||||||
|
function = "i2c4";
|
||||||
|
};
|
||||||
|
|
||||||
vin0_pins: vin0 {
|
vin0_pins: vin0 {
|
||||||
groups = "vin0_data8", "vin0_clk";
|
groups = "vin0_data8", "vin0_clk";
|
||||||
function = "vin0";
|
function = "vin0";
|
||||||
|
|
@ -277,6 +307,7 @@ &sdhi0 {
|
||||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
|
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
|
||||||
sd-uhs-sdr50;
|
sd-uhs-sdr50;
|
||||||
|
sd-uhs-sdr104;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -314,6 +345,11 @@ adv7180: endpoint {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
pinctrl-0 = <&i2c4_pins>;
|
||||||
|
pinctrl-names = "i2c-exio4";
|
||||||
|
};
|
||||||
|
|
||||||
&vin0 {
|
&vin0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
pinctrl-0 = <&vin0_pins>;
|
pinctrl-0 = <&vin0_pins>;
|
||||||
|
|
|
||||||
|
|
@ -319,7 +319,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
|
||||||
"ch12";
|
"ch12";
|
||||||
clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
|
clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
|
||||||
clock-names = "fck";
|
clock-names = "fck";
|
||||||
power-domains = <&cpg_clocks>;
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||||
#dma-cells = <1>;
|
#dma-cells = <1>;
|
||||||
dma-channels = <13>;
|
dma-channels = <13>;
|
||||||
};
|
};
|
||||||
|
|
@ -1262,7 +1262,7 @@ mstp5_clks: mstp5_clks@e6150144 {
|
||||||
mstp7_clks: mstp7_clks@e615014c {
|
mstp7_clks: mstp7_clks@e615014c {
|
||||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||||
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
||||||
clocks = <&mp_clk>, <&mp_clk>,
|
clocks = <&mp_clk>, <&hp_clk>,
|
||||||
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
||||||
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
||||||
<&zx_clk>;
|
<&zx_clk>;
|
||||||
|
|
@ -1377,6 +1377,11 @@ R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
prr: chipid@ff000044 {
|
||||||
|
compatible = "renesas,prr";
|
||||||
|
reg = <0 0xff000044 0 4>;
|
||||||
|
};
|
||||||
|
|
||||||
sysc: system-controller@e6180000 {
|
sysc: system-controller@e6180000 {
|
||||||
compatible = "renesas,r8a7794-sysc";
|
compatible = "renesas,r8a7794-sysc";
|
||||||
reg = <0 0xe6180000 0 0x0200>;
|
reg = <0 0xe6180000 0 0x0200>;
|
||||||
|
|
@ -1485,7 +1490,7 @@ rcar_sound: sound@ec500000 {
|
||||||
"mix.0", "mix.1",
|
"mix.0", "mix.1",
|
||||||
"dvc.0", "dvc.1",
|
"dvc.0", "dvc.1",
|
||||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||||
power-domains = <&cpg_clocks>;
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||||
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__
|
||||||
|
#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These power domain indices match the numbers of the interrupt bits
|
||||||
|
* representing the power areas in the various Interrupt Registers
|
||||||
|
* (e.g. SYSCISR, Interrupt Status Register)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define R8A7743_PD_CA15_CPU0 0
|
||||||
|
#define R8A7743_PD_CA15_CPU1 1
|
||||||
|
#define R8A7743_PD_CA15_SCU 12
|
||||||
|
#define R8A7743_PD_SGX 20
|
||||||
|
|
||||||
|
/* Always-on power area */
|
||||||
|
#define R8A7743_PD_ALWAYS_ON 32
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
|
||||||
|
#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These power domain indices match the numbers of the interrupt bits
|
||||||
|
* representing the power areas in the various Interrupt Registers
|
||||||
|
* (e.g. SYSCISR, Interrupt Status Register)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define R8A7745_PD_CA7_CPU0 5
|
||||||
|
#define R8A7745_PD_CA7_CPU1 6
|
||||||
|
#define R8A7745_PD_SGX 20
|
||||||
|
#define R8A7745_PD_CA7_SCU 21
|
||||||
|
|
||||||
|
/* Always-on power area */
|
||||||
|
#define R8A7745_PD_ALWAYS_ON 32
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */
|
||||||
Loading…
Reference in New Issue