dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake
Intel Elkhart Lake OSE (Offload Service Engine) provides few DMA controllers to the host. Enable them in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
parent
2b651ecfc3
commit
9e5ab0655e
|
@ -143,6 +143,11 @@ static const struct pci_device_id dw_pci_id_table[] = {
|
||||||
{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_data },
|
{ PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_data },
|
||||||
{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_data },
|
{ PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_data },
|
||||||
|
|
||||||
|
/* Elkhart Lake iDMA 32-bit (OSE DMA) */
|
||||||
|
{ PCI_VDEVICE(INTEL, 0x4bb4), (kernel_ulong_t)&idma32_pci_data },
|
||||||
|
{ PCI_VDEVICE(INTEL, 0x4bb5), (kernel_ulong_t)&idma32_pci_data },
|
||||||
|
{ PCI_VDEVICE(INTEL, 0x4bb6), (kernel_ulong_t)&idma32_pci_data },
|
||||||
|
|
||||||
/* Haswell */
|
/* Haswell */
|
||||||
{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_data },
|
{ PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_data },
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue