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arm64: dts: ls1012a: Add coreclk 

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Accordingly, update the clock-frequency in sysclk to 125M as platform
input clock.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Scott Wood 2017-06-05 11:28:22 +08:00 committed by Shawn Guo
parent 0fc9a6919c
commit 9ed5c17d4c
1 changed files with 10 additions and 2 deletions
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12
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
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@ -76,10 +76,17 @@ cpu0: cpu@0 {
sysclk: sysclk { sysclk: sysclk {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <100000000>; clock-frequency = <125000000>;
clock-output-names = "sysclk"; clock-output-names = "sysclk";
}; };
coreclk: coreclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "coreclk";
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
@ -248,7 +255,8 @@ clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen"; compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>; reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>; #clock-cells = <2>;
clocks = <&sysclk>; clocks = <&sysclk &coreclk>;
clock-names = "sysclk", "coreclk";
}; };
tmu: tmu@1f00000 { tmu: tmu@1f00000 {