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ARM: 8560/1: errata: Workaround errata A12 825619 / A17 852421 

The workaround for both errata is to set bit 24 in the diagnostic
register.  There are no known end-user bugs solved by fixing this
errata, but the fix is trivial and it seems sane to apply it.

The arguments for why this needs to be in the kernel are similar to the
arugments made in the patch "Workaround errata A12 818325/852422 A17
852423".

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Doug Anderson 2016-04-07 00:27:26 +01:00 committed by Russell King
parent 416bcf2159
commit 9f6f93543d
2 changed files with 29 additions and 0 deletions
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18
arch/arm/Kconfig
View File

@ -1210,6 +1210,24 @@ config ARM_ERRATA_821420
one is in the shadow of a branch or abort, can lead to a
deadlock when the VMOV instructions are issued out-of-order.
config ARM_ERRATA_825619
bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
depends on CPU_V7
help
This option enables the workaround for the 825619 Cortex-A12
(all revs) erratum. Within rare timing constraints, executing a
DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
and Device/Strongly-Ordered loads and stores might cause deadlock
config ARM_ERRATA_852421
bool "ARM errata: A17: DMB ST might fail to create order between stores"
depends on CPU_V7
help
This option enables the workaround for the 852421 Cortex-A17
(r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
execution of a DMB ST instruction might fail to properly order
stores from GroupA and stores from GroupB.
config ARM_ERRATA_852423
bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
depends on CPU_V7

11
arch/arm/mm/proc-v7.S
View File

@ -372,10 +372,21 @@ __ca12_errata:
mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
orr r10, r10, #1 << 1 @ set bit #1
mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
#endif
#ifdef CONFIG_ARM_ERRATA_825619
mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
orr r10, r10, #1 << 24 @ set bit #24
mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
b __errata_finish
__ca17_errata:
#ifdef CONFIG_ARM_ERRATA_852421
cmp r6, #0x12 @ only present up to r1p2
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
orrle r10, r10, #1 << 24 @ set bit #24
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_852423
cmp r6, #0x12 @ only present up to r1p2
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register