arm64: KVM: Add access handler for event type register
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER which is mapped to PMEVTYPERn or PMCCFILTR. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big endian. When writing to these registers, create a perf_event for the selected event type. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Shannon Zhao
Marc Zyngier
parent
7f76635871
commit
9feb21ac57
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@ -123,6 +123,9 @@ enum vcpu_sysreg {
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PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
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PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
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PMCCNTR_EL0, /* Cycle Counter Register */
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PMEVTYPER0_EL0, /* Event Type Register (0-30) */
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PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
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PMCCFILTR_EL0, /* Cycle Count Filter Register */
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PMCNTENSET_EL0, /* Count Enable Set Register */
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/* 32bit specific registers. Keep them at the end of the range */
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@ -563,6 +563,42 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
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return true;
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}
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static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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u64 idx, reg;
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if (!kvm_arm_pmu_v3_ready(vcpu))
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return trap_raz_wi(vcpu, p, r);
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if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
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/* PMXEVTYPER_EL0 */
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idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
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reg = PMEVTYPER0_EL0 + idx;
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} else if (r->CRn == 14 && (r->CRm & 12) == 12) {
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idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
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if (idx == ARMV8_PMU_CYCLE_IDX)
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reg = PMCCFILTR_EL0;
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else
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/* PMEVTYPERn_EL0 */
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reg = PMEVTYPER0_EL0 + idx;
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} else {
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BUG();
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}
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if (!pmu_counter_idx_valid(vcpu, idx))
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return false;
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if (p->is_write) {
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kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
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vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
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} else {
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p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
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}
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return true;
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}
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static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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@ -612,6 +648,13 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
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CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
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/* Macro to expand the PMEVTYPERn_EL0 register */
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#define PMU_PMEVTYPER_EL0(n) \
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/* PMEVTYPERn_EL0 */ \
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{ Op0(0b11), Op1(0b011), CRn(0b1110), \
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CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
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/*
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* Architected system registers.
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* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
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@ -808,7 +851,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
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/* PMXEVTYPER_EL0 */
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{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
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trap_raz_wi },
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access_pmu_evtyper },
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/* PMXEVCNTR_EL0 */
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{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
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access_pmu_evcntr },
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@ -858,6 +901,44 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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PMU_PMEVCNTR_EL0(28),
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PMU_PMEVCNTR_EL0(29),
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PMU_PMEVCNTR_EL0(30),
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/* PMEVTYPERn_EL0 */
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PMU_PMEVTYPER_EL0(0),
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PMU_PMEVTYPER_EL0(1),
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PMU_PMEVTYPER_EL0(2),
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PMU_PMEVTYPER_EL0(3),
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PMU_PMEVTYPER_EL0(4),
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PMU_PMEVTYPER_EL0(5),
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PMU_PMEVTYPER_EL0(6),
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PMU_PMEVTYPER_EL0(7),
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PMU_PMEVTYPER_EL0(8),
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PMU_PMEVTYPER_EL0(9),
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PMU_PMEVTYPER_EL0(10),
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PMU_PMEVTYPER_EL0(11),
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PMU_PMEVTYPER_EL0(12),
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PMU_PMEVTYPER_EL0(13),
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PMU_PMEVTYPER_EL0(14),
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PMU_PMEVTYPER_EL0(15),
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PMU_PMEVTYPER_EL0(16),
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PMU_PMEVTYPER_EL0(17),
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PMU_PMEVTYPER_EL0(18),
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PMU_PMEVTYPER_EL0(19),
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PMU_PMEVTYPER_EL0(20),
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PMU_PMEVTYPER_EL0(21),
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PMU_PMEVTYPER_EL0(22),
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PMU_PMEVTYPER_EL0(23),
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PMU_PMEVTYPER_EL0(24),
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PMU_PMEVTYPER_EL0(25),
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PMU_PMEVTYPER_EL0(26),
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PMU_PMEVTYPER_EL0(27),
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PMU_PMEVTYPER_EL0(28),
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PMU_PMEVTYPER_EL0(29),
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PMU_PMEVTYPER_EL0(30),
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/* PMCCFILTR_EL0
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* This register resets as unknown in 64bit mode while it resets as zero
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* in 32bit mode. Here we choose to reset it as zero for consistency.
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*/
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{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
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access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
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/* DACR32_EL2 */
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{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
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@ -1055,6 +1136,13 @@ static const struct sys_reg_desc cp14_64_regs[] = {
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CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evcntr }
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/* Macro to expand the PMEVTYPERn register */
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#define PMU_PMEVTYPER(n) \
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/* PMEVTYPERn */ \
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{ Op1(0), CRn(0b1110), \
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CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evtyper }
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/*
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* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
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* depending on the way they are accessed (as a 32bit or a 64bit
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@ -1091,7 +1179,7 @@ static const struct sys_reg_desc cp15_regs[] = {
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{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
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@ -1139,6 +1227,40 @@ static const struct sys_reg_desc cp15_regs[] = {
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PMU_PMEVCNTR(28),
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PMU_PMEVCNTR(29),
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PMU_PMEVCNTR(30),
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/* PMEVTYPERn */
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PMU_PMEVTYPER(0),
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PMU_PMEVTYPER(1),
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PMU_PMEVTYPER(2),
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PMU_PMEVTYPER(3),
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PMU_PMEVTYPER(4),
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PMU_PMEVTYPER(5),
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PMU_PMEVTYPER(6),
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PMU_PMEVTYPER(7),
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PMU_PMEVTYPER(8),
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PMU_PMEVTYPER(9),
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PMU_PMEVTYPER(10),
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PMU_PMEVTYPER(11),
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PMU_PMEVTYPER(12),
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PMU_PMEVTYPER(13),
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PMU_PMEVTYPER(14),
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PMU_PMEVTYPER(15),
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PMU_PMEVTYPER(16),
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PMU_PMEVTYPER(17),
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PMU_PMEVTYPER(18),
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PMU_PMEVTYPER(19),
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PMU_PMEVTYPER(20),
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PMU_PMEVTYPER(21),
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PMU_PMEVTYPER(22),
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PMU_PMEVTYPER(23),
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PMU_PMEVTYPER(24),
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PMU_PMEVTYPER(25),
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PMU_PMEVTYPER(26),
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PMU_PMEVTYPER(27),
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PMU_PMEVTYPER(28),
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PMU_PMEVTYPER(29),
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PMU_PMEVTYPER(30),
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/* PMCCFILTR */
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{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
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};
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static const struct sys_reg_desc cp15_64_regs[] = {
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