PCI: keystone: Use uniform function naming convention
No functional change. Some function names begin with ks_dw_pcie_* and some function names begin with ks_pcie_*. Modify it so that all function names begin with ks_pcie_*. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Kishon Vijay Abraham I
Lorenzo Pieralisi
parent
c81ab80136
commit
a1cabd2b42
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@ -118,7 +118,7 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
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*bit_pos = offset >> 3;
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}
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static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
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static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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@ -126,17 +126,18 @@ static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
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return ks_pcie->app.start + MSI_IRQ;
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}
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static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
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static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
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{
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return readl(ks_pcie->va_app_base + offset);
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}
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static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
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static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
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u32 val)
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{
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writel(val, ks_pcie->va_app_base + offset);
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}
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static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
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static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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@ -144,7 +145,7 @@ static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
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u32 pending, vector;
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int src, virq;
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pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
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pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
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/*
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* MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
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@ -161,7 +162,7 @@ static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
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}
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}
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static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
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static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
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{
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u32 reg_offset, bit_pos;
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struct keystone_pcie *ks_pcie;
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@ -171,55 +172,55 @@ static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
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ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
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BIT(bit_pos));
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ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
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ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
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BIT(bit_pos));
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ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
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}
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static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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u32 reg_offset, bit_pos;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
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BIT(bit_pos));
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ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
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BIT(bit_pos));
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}
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static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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u32 reg_offset, bit_pos;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
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BIT(bit_pos));
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ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
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BIT(bit_pos));
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}
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static int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
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static int ks_pcie_msi_host_init(struct pcie_port *pp)
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{
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return dw_pcie_allocate_domains(pp);
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}
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static void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
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static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
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{
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int i;
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for (i = 0; i < PCI_NUM_INTX; i++)
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ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
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ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
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}
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static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
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int offset)
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static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
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int offset)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct device *dev = pci->dev;
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u32 pending;
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int virq;
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pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
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pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
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if (BIT(0) & pending) {
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virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
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@ -228,19 +229,19 @@ static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
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}
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/* EOI the INTx interrupt */
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ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
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ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
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}
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static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
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static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
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{
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ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
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ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
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}
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static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
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static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
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{
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u32 status;
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status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
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status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
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if (!status)
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return IRQ_NONE;
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@ -249,83 +250,83 @@ static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
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status);
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/* Ack the IRQ; status bits are RW1C */
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ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
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ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
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return IRQ_HANDLED;
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}
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static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
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static void ks_pcie_ack_legacy_irq(struct irq_data *d)
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{
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}
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static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
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static void ks_pcie_mask_legacy_irq(struct irq_data *d)
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{
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}
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static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
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static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
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{
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}
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static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
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static struct irq_chip ks_pcie_legacy_irq_chip = {
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.name = "Keystone-PCI-Legacy-IRQ",
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.irq_ack = ks_dw_pcie_ack_legacy_irq,
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.irq_mask = ks_dw_pcie_mask_legacy_irq,
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.irq_unmask = ks_dw_pcie_unmask_legacy_irq,
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.irq_ack = ks_pcie_ack_legacy_irq,
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.irq_mask = ks_pcie_mask_legacy_irq,
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.irq_unmask = ks_pcie_unmask_legacy_irq,
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};
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static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
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unsigned int irq,
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irq_hw_number_t hw_irq)
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static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
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unsigned int irq,
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irq_hw_number_t hw_irq)
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{
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irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
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irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
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.map = ks_dw_pcie_init_legacy_irq_map,
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static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
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.map = ks_pcie_init_legacy_irq_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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/**
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* ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
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* ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
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* registers
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
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static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
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do {
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (!(val & DBI_CS2_EN_VAL));
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}
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/**
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* ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
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* ks_pcie_clear_dbi_mode() - Disable DBI mode
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
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do {
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (val & DBI_CS2_EN_VAL);
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}
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static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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@ -334,26 +335,26 @@ static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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u32 val;
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/* Disable BARs for inbound access */
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ks_dw_pcie_set_dbi_mode(ks_pcie);
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ks_pcie_set_dbi_mode(ks_pcie);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
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ks_dw_pcie_clear_dbi_mode(ks_pcie);
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ks_pcie_clear_dbi_mode(ks_pcie);
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/* Set outbound translation size per window division */
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ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
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ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
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tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
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/* Using Direct 1:1 mapping of RC <-> PCI memory space */
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for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
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ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
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ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
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start += tr_size;
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}
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/* Enable OB translation */
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
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}
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/**
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@ -394,13 +395,13 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
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if (bus != 1)
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regval |= BIT(24);
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ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
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ks_pcie_app_writel(ks_pcie, CFG_SETUP, regval);
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return pp->va_cfg0_base;
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}
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static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 *val)
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static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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@ -412,9 +413,9 @@ static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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return dw_pcie_read(addr + where, size, val);
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}
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static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 val)
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static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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@ -427,23 +428,23 @@ static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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}
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/**
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* ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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* ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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*
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* This sets BAR0 to enable inbound access for MSI_IRQ register
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*/
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static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
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static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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/* Configure and set up BAR0 */
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ks_dw_pcie_set_dbi_mode(ks_pcie);
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ks_pcie_set_dbi_mode(ks_pcie);
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/* Enable BAR0 */
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
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ks_dw_pcie_clear_dbi_mode(ks_pcie);
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ks_pcie_clear_dbi_mode(ks_pcie);
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/*
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* For BAR0, just setting bus address for inbound writes (MSI) should
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@ -453,9 +454,9 @@ static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
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}
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/**
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* ks_dw_pcie_link_up() - Check if link up
|
||||
* ks_pcie_link_up() - Check if link up
|
||||
*/
|
||||
static int ks_dw_pcie_link_up(struct dw_pcie *pci)
|
||||
static int ks_pcie_link_up(struct dw_pcie *pci)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
|
|
@ -463,28 +464,28 @@ static int ks_dw_pcie_link_up(struct dw_pcie *pci)
|
|||
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
|
||||
}
|
||||
|
||||
static void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
|
||||
static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Disable Link training */
|
||||
val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
|
||||
val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
|
||||
val &= ~LTSSM_EN_VAL;
|
||||
ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
|
||||
ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
|
||||
|
||||
/* Initiate Link Training */
|
||||
val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
|
||||
ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
|
||||
val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
|
||||
ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
|
||||
}
|
||||
|
||||
/**
|
||||
* ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
|
||||
* ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware
|
||||
*
|
||||
* Ioremap the register resources, initialize legacy irq domain
|
||||
* and call dw_pcie_v3_65_host_init() API to initialize the Keystone
|
||||
* PCI host controller.
|
||||
*/
|
||||
static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie)
|
||||
static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie)
|
||||
{
|
||||
struct dw_pcie *pci = ks_pcie->pci;
|
||||
struct pcie_port *pp = &pci->pp;
|
||||
|
|
@ -517,7 +518,7 @@ static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie)
|
|||
ks_pcie->legacy_irq_domain =
|
||||
irq_domain_add_linear(ks_pcie->legacy_intc_np,
|
||||
PCI_NUM_INTX,
|
||||
&ks_dw_pcie_legacy_irq_domain_ops,
|
||||
&ks_pcie_legacy_irq_domain_ops,
|
||||
NULL);
|
||||
if (!ks_pcie->legacy_irq_domain) {
|
||||
dev_err(dev, "Failed to add irq domain for legacy irqs\n");
|
||||
|
|
@ -527,7 +528,7 @@ static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie)
|
|||
return dw_pcie_host_init(pp);
|
||||
}
|
||||
|
||||
static void quirk_limit_mrrs(struct pci_dev *dev)
|
||||
static void ks_pcie_quirk(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_bus *bus = dev->bus;
|
||||
struct pci_dev *bridge;
|
||||
|
|
@ -568,7 +569,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
|
|||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
|
||||
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
|
||||
|
||||
static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
|
||||
{
|
||||
|
|
@ -580,7 +581,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
|
|||
return 0;
|
||||
}
|
||||
|
||||
ks_dw_pcie_initiate_link_train(ks_pcie);
|
||||
ks_pcie_initiate_link_train(ks_pcie);
|
||||
|
||||
/* check if the link is up or not */
|
||||
if (!dw_pcie_wait_for_link(pci))
|
||||
|
|
@ -607,7 +608,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
|
|||
* ack operation.
|
||||
*/
|
||||
chained_irq_enter(chip, desc);
|
||||
ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
|
||||
ks_pcie_handle_msi_irq(ks_pcie, offset);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
|
|
@ -636,7 +637,7 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
|
|||
* ack operation.
|
||||
*/
|
||||
chained_irq_enter(chip, desc);
|
||||
ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
|
||||
ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
|
|
@ -708,7 +709,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
|
|||
ks_pcie_legacy_irq_handler,
|
||||
ks_pcie);
|
||||
}
|
||||
ks_dw_pcie_enable_legacy_irqs(ks_pcie);
|
||||
ks_pcie_enable_legacy_irqs(ks_pcie);
|
||||
|
||||
/* MSI IRQ */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
|
|
@ -720,7 +721,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
|
|||
}
|
||||
|
||||
if (ks_pcie->error_irq > 0)
|
||||
ks_dw_pcie_enable_error_irq(ks_pcie);
|
||||
ks_pcie_enable_error_irq(ks_pcie);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -728,8 +729,8 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
|
|||
* bus error instead of returning 0xffffffff. This handler always returns 0
|
||||
* for this kind of faults.
|
||||
*/
|
||||
static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
|
||||
struct pt_regs *regs)
|
||||
static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
unsigned long instr = *(unsigned long *) instruction_pointer(regs);
|
||||
|
||||
|
|
@ -751,7 +752,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
|
|||
dw_pcie_setup_rc(pp);
|
||||
|
||||
ks_pcie_establish_link(ks_pcie);
|
||||
ks_dw_pcie_setup_rc_app_regs(ks_pcie);
|
||||
ks_pcie_setup_rc_app_regs(ks_pcie);
|
||||
ks_pcie_setup_interrupts(ks_pcie);
|
||||
writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
|
||||
pci->dbi_base + PCI_IO_BASE);
|
||||
|
|
@ -763,33 +764,33 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
|
|||
* PCIe access errors that result into OCP errors are caught by ARM as
|
||||
* "External aborts"
|
||||
*/
|
||||
hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
|
||||
hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
|
||||
"Asynchronous external abort");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
|
||||
.rd_other_conf = ks_dw_pcie_rd_other_conf,
|
||||
.wr_other_conf = ks_dw_pcie_wr_other_conf,
|
||||
static const struct dw_pcie_host_ops ks_pcie_host_ops = {
|
||||
.rd_other_conf = ks_pcie_rd_other_conf,
|
||||
.wr_other_conf = ks_pcie_wr_other_conf,
|
||||
.host_init = ks_pcie_host_init,
|
||||
.msi_set_irq = ks_dw_pcie_msi_set_irq,
|
||||
.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
|
||||
.get_msi_addr = ks_dw_pcie_get_msi_addr,
|
||||
.msi_host_init = ks_dw_pcie_msi_host_init,
|
||||
.msi_irq_ack = ks_dw_pcie_msi_irq_ack,
|
||||
.scan_bus = ks_dw_pcie_v3_65_scan_bus,
|
||||
.msi_set_irq = ks_pcie_msi_set_irq,
|
||||
.msi_clear_irq = ks_pcie_msi_clear_irq,
|
||||
.get_msi_addr = ks_pcie_get_msi_addr,
|
||||
.msi_host_init = ks_pcie_msi_host_init,
|
||||
.msi_irq_ack = ks_pcie_msi_irq_ack,
|
||||
.scan_bus = ks_pcie_v3_65_scan_bus,
|
||||
};
|
||||
|
||||
static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
|
||||
static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
|
||||
{
|
||||
struct keystone_pcie *ks_pcie = priv;
|
||||
|
||||
return ks_dw_pcie_handle_error_irq(ks_pcie);
|
||||
return ks_pcie_handle_error_irq(ks_pcie);
|
||||
}
|
||||
|
||||
static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
|
||||
struct platform_device *pdev)
|
||||
static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct dw_pcie *pci = ks_pcie->pci;
|
||||
struct pcie_port *pp = &pci->pp;
|
||||
|
|
@ -818,7 +819,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
|
|||
if (ks_pcie->error_irq <= 0)
|
||||
dev_info(dev, "no error IRQ defined\n");
|
||||
else {
|
||||
ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
|
||||
ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler,
|
||||
IRQF_SHARED, "pcie-error-irq", ks_pcie);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to request error IRQ %d\n",
|
||||
|
|
@ -827,8 +828,8 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
|
|||
}
|
||||
}
|
||||
|
||||
pp->ops = &keystone_pcie_host_ops;
|
||||
ret = ks_dw_pcie_host_init(ks_pcie);
|
||||
pp->ops = &ks_pcie_host_ops;
|
||||
ret = ks_pcie_dw_host_init(ks_pcie);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
|
|
@ -845,8 +846,8 @@ static const struct of_device_id ks_pcie_of_match[] = {
|
|||
{ },
|
||||
};
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = ks_dw_pcie_link_up,
|
||||
static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
|
||||
.link_up = ks_pcie_link_up,
|
||||
};
|
||||
|
||||
static int __exit ks_pcie_remove(struct platform_device *pdev)
|
||||
|
|
@ -877,7 +878,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
|
||||
pci->dev = dev;
|
||||
pci->ops = &dw_pcie_ops;
|
||||
pci->ops = &ks_pcie_dw_pcie_ops;
|
||||
|
||||
ks_pcie->pci = pci;
|
||||
|
||||
|
|
@ -912,7 +913,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ks_add_pcie_port(ks_pcie, pdev);
|
||||
ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
|
||||
if (ret < 0)
|
||||
goto fail_clk;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue