arm64/kernel: don't ban ADRP to work around Cortex-A53 erratum #843419
Working around Cortex-A53 erratum #843419 involves special handling of ADRP instructions that end up in the last two instruction slots of a 4k page, or whose output register gets overwritten without having been read. (Note that the latter instruction sequence is never emitted by a properly functioning compiler, which is why it is disregarded by the handling of the same erratum in the bfd.ld linker which we rely on for the core kernel) Normally, this gets taken care of by the linker, which can spot such sequences at final link time, and insert a veneer if the ADRP ends up at a vulnerable offset. However, linux kernel modules are partially linked ELF objects, and so there is no 'final link time' other than the runtime loading of the module, at which time all the static relocations are resolved. For this reason, we have implemented the #843419 workaround for modules by avoiding ADRP instructions altogether, by using the large C model, and by passing -mpc-relative-literal-loads to recent versions of GCC that may emit adrp/ldr pairs to perform literal loads. However, this workaround forces us to keep literal data mixed with the instructions in the executable .text segment, and literal data may inadvertently turn into an exploitable speculative gadget depending on the relative offsets of arbitrary symbols. So let's reimplement this workaround in a way that allows us to switch back to the small C model, and to drop the -mpc-relative-literal-loads GCC switch, by patching affected ADRP instructions at runtime: - ADRP instructions that do not appear at 4k relative offset 0xff8 or 0xffc are ignored - ADRP instructions that are within 1 MB of their target symbol are converted into ADR instructions - remaining ADRP instructions are redirected via a veneer that performs the load using an unaffected movn/movk sequence. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [will: tidied up ADRP -> ADR instruction patching.] [will: use ULL suffix for 64-bit immediate] Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Ard Biesheuvel
Will Deacon
parent
f2b9ba871b
commit
a257e02579
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@ -456,12 +456,12 @@ config ARM64_ERRATUM_845719
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config ARM64_ERRATUM_843419
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bool "Cortex-A53: 843419: A load or store might access an incorrect address"
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default y
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select ARM64_MODULE_CMODEL_LARGE if MODULES
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select ARM64_MODULE_PLTS if MODULES
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help
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This option links the kernel with '--fix-cortex-a53-843419' and
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builds modules using the large memory model in order to avoid the use
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of the ADRP instruction, which can cause a subsequent memory access
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to use an incorrect address on Cortex-A53 parts up to r0p4.
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enables PLT support to replace certain ADRP instructions, which can
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cause subsequent memory accesses to use an incorrect address on
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Cortex-A53 parts up to r0p4.
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If unsure, say Y.
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@ -1105,9 +1105,6 @@ config ARM64_SVE
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To enable use of this extension on CPUs that implement it, say Y.
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config ARM64_MODULE_CMODEL_LARGE
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bool
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config ARM64_MODULE_PLTS
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bool
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select HAVE_MOD_ARCH_SPECIFIC
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@ -51,7 +51,6 @@ endif
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KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
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KBUILD_CFLAGS += $(call cc-option, -mpc-relative-literal-loads)
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KBUILD_AFLAGS += $(lseinstr) $(brokengasinst)
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KBUILD_CFLAGS += $(call cc-option,-mabi=lp64)
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@ -77,10 +76,6 @@ endif
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CHECKFLAGS += -D__aarch64__ -m64
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ifeq ($(CONFIG_ARM64_MODULE_CMODEL_LARGE), y)
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KBUILD_CFLAGS_MODULE += -mcmodel=large
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endif
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ifeq ($(CONFIG_ARM64_MODULE_PLTS),y)
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KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/arm64/kernel/module.lds
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endif
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@ -39,6 +39,8 @@ struct mod_arch_specific {
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u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
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Elf64_Sym *sym);
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u64 module_emit_adrp_veneer(struct module *mod, void *loc, u64 val);
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#ifdef CONFIG_RANDOMIZE_BASE
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extern u64 module_alloc_base;
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#else
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@ -42,6 +42,47 @@ u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
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return (u64)&plt[i];
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}
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#ifdef CONFIG_ARM64_ERRATUM_843419
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u64 module_emit_adrp_veneer(struct module *mod, void *loc, u64 val)
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{
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struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
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&mod->arch.init;
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struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr;
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int i = pltsec->plt_num_entries++;
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u32 mov0, mov1, mov2, br;
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int rd;
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if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
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return 0;
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/* get the destination register of the ADRP instruction */
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD,
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le32_to_cpup((__le32 *)loc));
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/* generate the veneer instructions */
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mov0 = aarch64_insn_gen_movewide(rd, (u16)~val, 0,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_INVERSE);
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mov1 = aarch64_insn_gen_movewide(rd, (u16)(val >> 16), 16,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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mov2 = aarch64_insn_gen_movewide(rd, (u16)(val >> 32), 32,
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AARCH64_INSN_VARIANT_64BIT,
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AARCH64_INSN_MOVEWIDE_KEEP);
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br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4,
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AARCH64_INSN_BRANCH_NOLINK);
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plt[i] = (struct plt_entry){
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cpu_to_le32(mov0),
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cpu_to_le32(mov1),
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cpu_to_le32(mov2),
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cpu_to_le32(br)
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};
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return (u64)&plt[i];
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}
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#endif
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#define cmp_3way(a,b) ((a) < (b) ? -1 : (a) > (b))
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static int cmp_rela(const void *a, const void *b)
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@ -69,16 +110,21 @@ static bool duplicate_rel(const Elf64_Rela *rela, int num)
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}
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static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
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Elf64_Word dstidx)
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Elf64_Word dstidx, Elf_Shdr *dstsec)
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{
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unsigned int ret = 0;
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Elf64_Sym *s;
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int i;
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for (i = 0; i < num; i++) {
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u64 min_align;
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switch (ELF64_R_TYPE(rela[i].r_info)) {
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case R_AARCH64_JUMP26:
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case R_AARCH64_CALL26:
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if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
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break;
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/*
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* We only have to consider branch targets that resolve
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* to symbols that are defined in a different section.
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@ -110,6 +156,40 @@ static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
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if (rela[i].r_addend != 0 || !duplicate_rel(rela, i))
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ret++;
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break;
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case R_AARCH64_ADR_PREL_PG_HI21_NC:
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case R_AARCH64_ADR_PREL_PG_HI21:
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419))
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break;
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/*
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* Determine the minimal safe alignment for this ADRP
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* instruction: the section alignment at which it is
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* guaranteed not to appear at a vulnerable offset.
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*
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* This comes down to finding the least significant zero
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* bit in bits [11:3] of the section offset, and
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* increasing the section's alignment so that the
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* resulting address of this instruction is guaranteed
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* to equal the offset in that particular bit (as well
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* as all less signficant bits). This ensures that the
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* address modulo 4 KB != 0xfff8 or 0xfffc (which would
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* have all ones in bits [11:3])
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*/
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min_align = 2ULL << ffz(rela[i].r_offset | 0x7);
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/*
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* Allocate veneer space for each ADRP that may appear
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* at a vulnerable offset nonetheless. At relocation
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* time, some of these will remain unused since some
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* ADRP instructions can be patched to ADR instructions
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* instead.
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*/
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if (min_align > SZ_4K)
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ret++;
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else
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dstsec->sh_addralign = max(dstsec->sh_addralign,
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min_align);
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break;
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}
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}
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return ret;
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@ -167,10 +247,10 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
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if (strncmp(secstrings + dstsec->sh_name, ".init", 5) != 0)
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core_plts += count_plts(syms, rels, numrels,
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sechdrs[i].sh_info);
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sechdrs[i].sh_info, dstsec);
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else
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init_plts += count_plts(syms, rels, numrels,
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sechdrs[i].sh_info);
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sechdrs[i].sh_info, dstsec);
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}
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mod->arch.core.plt->sh_type = SHT_NOBITS;
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@ -198,6 +198,33 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
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return 0;
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}
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static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val)
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{
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u32 insn;
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
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((u64)place & 0xfff) < 0xff8)
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return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
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AARCH64_INSN_IMM_ADR);
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/* patch ADRP to ADR if it is in range */
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if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
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AARCH64_INSN_IMM_ADR)) {
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insn = le32_to_cpu(*place);
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insn &= ~BIT(31);
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} else {
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/* out of range for ADR -> emit a veneer */
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val = module_emit_adrp_veneer(mod, place, val & ~0xfff);
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if (!val)
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return -ENOEXEC;
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insn = aarch64_insn_gen_branch_imm((u64)place, val,
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AARCH64_INSN_BRANCH_NOLINK);
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}
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*place = cpu_to_le32(insn);
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return 0;
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}
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int apply_relocate_add(Elf64_Shdr *sechdrs,
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const char *strtab,
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unsigned int symindex,
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@ -337,14 +364,13 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
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AARCH64_INSN_IMM_ADR);
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break;
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#ifndef CONFIG_ARM64_ERRATUM_843419
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case R_AARCH64_ADR_PREL_PG_HI21_NC:
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overflow_check = false;
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case R_AARCH64_ADR_PREL_PG_HI21:
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ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
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AARCH64_INSN_IMM_ADR);
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ovf = reloc_insn_adrp(me, loc, val);
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if (ovf && ovf != -ERANGE)
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return ovf;
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break;
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#endif
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case R_AARCH64_ADD_ABS_LO12_NC:
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case R_AARCH64_LDST8_ABS_LO12_NC:
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overflow_check = false;
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@ -28,6 +28,7 @@ asmlinkage u64 absolute_data16(void);
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asmlinkage u64 signed_movw(void);
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asmlinkage u64 unsigned_movw(void);
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asmlinkage u64 relative_adrp(void);
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asmlinkage u64 relative_adrp_far(void);
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asmlinkage u64 relative_adr(void);
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asmlinkage u64 relative_data64(void);
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asmlinkage u64 relative_data32(void);
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@ -43,9 +44,8 @@ static struct {
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{ "R_AARCH64_ABS16", absolute_data16, UL(SYM16_ABS_VAL) },
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{ "R_AARCH64_MOVW_SABS_Gn", signed_movw, UL(SYM64_ABS_VAL) },
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{ "R_AARCH64_MOVW_UABS_Gn", unsigned_movw, UL(SYM64_ABS_VAL) },
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#ifndef CONFIG_ARM64_ERRATUM_843419
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{ "R_AARCH64_ADR_PREL_PG_HI21", relative_adrp, (u64)&sym64_rel },
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#endif
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{ "R_AARCH64_ADR_PREL_PG_HI21", relative_adrp_far, (u64)&printk },
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{ "R_AARCH64_ADR_PREL_LO21", relative_adr, (u64)&sym64_rel },
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{ "R_AARCH64_PREL64", relative_data64, (u64)&sym64_rel },
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{ "R_AARCH64_PREL32", relative_data32, (u64)&sym64_rel },
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@ -43,15 +43,21 @@ ENTRY(unsigned_movw)
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ret
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ENDPROC(unsigned_movw)
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#ifndef CONFIG_ARM64_ERRATUM_843419
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.align 12
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.space 0xff8
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ENTRY(relative_adrp)
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adrp x0, sym64_rel
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add x0, x0, #:lo12:sym64_rel
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ret
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ENDPROC(relative_adrp)
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#endif
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.align 12
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.space 0xffc
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ENTRY(relative_adrp_far)
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adrp x0, printk
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add x0, x0, #:lo12:printk
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ret
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ENDPROC(relative_adrp_far)
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ENTRY(relative_adr)
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adr x0, sym64_rel
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