mmc: mediatek: add MT8183 MMC driver support
MT8183 puts the tune register at top layer, so need add new code to support it. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Chaotian Jing
Ulf Hansson
parent
86601d0eac
commit
a2e6d1f6b3
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@ -86,6 +86,13 @@
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#define EMMC50_CFG3 0x220
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#define SDC_FIFO_CFG 0x228
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/*--------------------------------------------------------------------------*/
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/* Top Pad Register Offset */
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/*--------------------------------------------------------------------------*/
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#define EMMC_TOP_CONTROL 0x00
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#define EMMC_TOP_CMD 0x04
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#define EMMC50_PAD_DS_TUNE 0x0c
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/*--------------------------------------------------------------------------*/
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/* Register Mask */
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/*--------------------------------------------------------------------------*/
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@ -261,6 +268,23 @@
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#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
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#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
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/* EMMC_TOP_CONTROL mask */
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#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
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#define DELAY_EN (0x1 << 1) /* RW */
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#define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
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#define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
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#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
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#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
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#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
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#define SDC_RX_ENH_EN (0x1 << 15) /* TW */
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/* EMMC_TOP_CMD mask */
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#define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
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#define PAD_CMD_RXDLY (0x1f << 5) /* RW */
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#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
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#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
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#define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
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#define REQ_CMD_EIO (0x1 << 0)
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#define REQ_CMD_TMO (0x1 << 1)
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#define REQ_DAT_ERR (0x1 << 2)
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@ -333,6 +357,9 @@ struct msdc_save_para {
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u32 emmc50_cfg0;
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u32 emmc50_cfg3;
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u32 sdc_fifo_cfg;
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u32 emmc_top_control;
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u32 emmc_top_cmd;
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u32 emmc50_pad_ds_tune;
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};
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struct mtk_mmc_compatible {
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@ -351,6 +378,8 @@ struct msdc_tune_para {
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u32 iocon;
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u32 pad_tune;
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u32 pad_cmd_tune;
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u32 emmc_top_control;
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u32 emmc_top_cmd;
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};
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struct msdc_delay_phase {
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@ -372,6 +401,7 @@ struct msdc_host {
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int error;
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void __iomem *base; /* host base address */
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void __iomem *top_base; /* host top register base address */
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struct msdc_dma dma; /* dma channel */
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u64 dma_mask;
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@ -429,6 +459,18 @@ static const struct mtk_mmc_compatible mt8173_compat = {
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.support_64g = false,
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};
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static const struct mtk_mmc_compatible mt8183_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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.pad_tune_reg = MSDC_PAD_TUNE0,
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.async_fifo = true,
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.data_tune = true,
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.busy_check = true,
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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@ -468,6 +510,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
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static const struct of_device_id msdc_of_ids[] = {
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{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
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{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
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{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
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{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
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{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
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{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
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@ -777,12 +820,28 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
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*/
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if (host->mmc->actual_clock <= 52000000) {
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writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
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writel(host->def_tune_para.pad_tune, host->base + tune_reg);
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if (host->top_base) {
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writel(host->def_tune_para.emmc_top_control,
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host->top_base + EMMC_TOP_CONTROL);
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writel(host->def_tune_para.emmc_top_cmd,
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host->top_base + EMMC_TOP_CMD);
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} else {
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writel(host->def_tune_para.pad_tune,
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host->base + tune_reg);
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}
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} else {
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writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
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writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
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writel(host->saved_tune_para.pad_cmd_tune,
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host->base + PAD_CMD_TUNE);
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if (host->top_base) {
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writel(host->saved_tune_para.emmc_top_control,
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host->top_base + EMMC_TOP_CONTROL);
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writel(host->saved_tune_para.emmc_top_cmd,
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host->top_base + EMMC_TOP_CMD);
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} else {
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writel(host->saved_tune_para.pad_tune,
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host->base + tune_reg);
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}
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}
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if (timing == MMC_TIMING_MMC_HS400 &&
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@ -1355,7 +1414,12 @@ static void msdc_init_hw(struct msdc_host *host)
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val = readl(host->base + MSDC_INT);
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writel(val, host->base + MSDC_INT);
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writel(0, host->base + tune_reg);
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if (host->top_base) {
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writel(0, host->top_base + EMMC_TOP_CONTROL);
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writel(0, host->top_base + EMMC_TOP_CMD);
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} else {
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writel(0, host->base + tune_reg);
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}
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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@ -1379,8 +1443,12 @@ static void msdc_init_hw(struct msdc_host *host)
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sdr_set_field(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_RESPWAIT, 3);
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if (host->dev_comp->enhance_rx) {
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sdr_set_bits(host->base + SDC_ADV_CFG0,
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SDC_RX_ENHANCE_EN);
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if (host->top_base)
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sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
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SDC_RX_ENH_EN);
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else
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sdr_set_bits(host->base + SDC_ADV_CFG0,
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SDC_RX_ENHANCE_EN);
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} else {
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sdr_set_field(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_RESPSTSENSEL, 2);
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@ -1398,11 +1466,26 @@ static void msdc_init_hw(struct msdc_host *host)
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sdr_set_bits(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_SUPPORT_64G);
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if (host->dev_comp->data_tune) {
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sdr_set_bits(host->base + tune_reg,
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MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
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if (host->top_base) {
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sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY_SEL);
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sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
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DATA_K_VALUE_SEL);
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sdr_set_bits(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RD_RXDLY_SEL);
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} else {
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sdr_set_bits(host->base + tune_reg,
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MSDC_PAD_TUNE_RD_SEL |
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MSDC_PAD_TUNE_CMD_SEL);
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}
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} else {
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/* choose clock tune */
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sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
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if (host->top_base)
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sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
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PAD_RXDLY_SEL);
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else
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sdr_set_bits(host->base + tune_reg,
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MSDC_PAD_TUNE_RXDLYSEL);
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}
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/* Configure to enable SDIO mode.
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@ -1417,9 +1500,20 @@ static void msdc_init_hw(struct msdc_host *host)
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sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
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host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
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host->def_tune_para.pad_tune = readl(host->base + tune_reg);
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host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
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host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
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if (host->top_base) {
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host->def_tune_para.emmc_top_control =
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readl(host->top_base + EMMC_TOP_CONTROL);
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host->def_tune_para.emmc_top_cmd =
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readl(host->top_base + EMMC_TOP_CMD);
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host->saved_tune_para.emmc_top_control =
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readl(host->top_base + EMMC_TOP_CONTROL);
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host->saved_tune_para.emmc_top_cmd =
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readl(host->top_base + EMMC_TOP_CMD);
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} else {
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host->def_tune_para.pad_tune = readl(host->base + tune_reg);
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host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
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}
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dev_dbg(host->dev, "init hardware done!");
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}
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@ -1587,8 +1681,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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* but sometimes it may fail. To make sure the parameters are
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@ -1612,8 +1710,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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* but sometimes it may fail. To make sure the parameters are
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@ -1637,13 +1739,23 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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final_maxlen = final_fall_delay.maxlen;
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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if (host->top_base)
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sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
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final_rise_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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if (host->top_base)
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sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
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final_fall_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
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@ -1728,8 +1840,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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@ -1743,8 +1859,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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@ -1756,16 +1876,26 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY,
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final_rise_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY,
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final_fall_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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@ -1793,10 +1923,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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if (host->top_base) {
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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} else {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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}
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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@ -1811,10 +1948,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
|
|||
sdr_set_bits(host->base + MSDC_IOCON,
|
||||
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
|
||||
for (i = 0; i < PAD_DELAY_MAX; i++) {
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_CMDRDLY, i);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY, i);
|
||||
if (host->top_base) {
|
||||
sdr_set_field(host->top_base + EMMC_TOP_CMD,
|
||||
PAD_CMD_RXDLY, i);
|
||||
sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
|
||||
PAD_DAT_RD_RXDLY, i);
|
||||
} else {
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_CMDRDLY, i);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY, i);
|
||||
}
|
||||
ret = mmc_send_tuning(mmc, opcode, NULL);
|
||||
if (!ret)
|
||||
fall_delay |= (1 << i);
|
||||
|
|
@ -1827,24 +1971,26 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
|
|||
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
|
||||
sdr_clr_bits(host->base + MSDC_IOCON,
|
||||
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
|
||||
sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
final_rise_delay.final_phase);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY,
|
||||
final_rise_delay.final_phase);
|
||||
final_delay = final_rise_delay.final_phase;
|
||||
} else {
|
||||
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
|
||||
sdr_set_bits(host->base + MSDC_IOCON,
|
||||
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
|
||||
sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
final_fall_delay.final_phase);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY,
|
||||
final_fall_delay.final_phase);
|
||||
final_delay = final_fall_delay.final_phase;
|
||||
}
|
||||
|
||||
if (host->top_base) {
|
||||
sdr_set_field(host->top_base + EMMC_TOP_CMD,
|
||||
PAD_CMD_RXDLY, final_delay);
|
||||
sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
|
||||
PAD_DAT_RD_RXDLY, final_delay);
|
||||
} else {
|
||||
sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
|
||||
final_delay);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY, final_delay);
|
||||
}
|
||||
|
||||
dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
|
||||
return final_delay == 0xff ? -EIO : 0;
|
||||
}
|
||||
|
|
@ -1860,8 +2006,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
|||
if (host->hs400_mode) {
|
||||
sdr_clr_bits(host->base + MSDC_IOCON,
|
||||
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY, 0);
|
||||
if (host->top_base)
|
||||
sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
|
||||
PAD_DAT_RD_RXDLY, 0);
|
||||
else
|
||||
sdr_set_field(host->base + tune_reg,
|
||||
MSDC_PAD_TUNE_DATRRDLY, 0);
|
||||
}
|
||||
goto tune_done;
|
||||
}
|
||||
|
|
@ -1884,6 +2034,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
|||
host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
|
||||
host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
|
||||
host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
|
||||
if (host->top_base) {
|
||||
host->saved_tune_para.emmc_top_control = readl(host->top_base +
|
||||
EMMC_TOP_CONTROL);
|
||||
host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
|
||||
EMMC_TOP_CMD);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1892,7 +2048,11 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
struct msdc_host *host = mmc_priv(mmc);
|
||||
host->hs400_mode = true;
|
||||
|
||||
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
|
||||
if (host->top_base)
|
||||
writel(host->hs400_ds_delay,
|
||||
host->top_base + EMMC50_PAD_DS_TUNE);
|
||||
else
|
||||
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
|
||||
/* hs400 mode must set it to 0 */
|
||||
sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
|
||||
/* to improve read performance, set outstanding to 2 */
|
||||
|
|
@ -1975,6 +2135,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
|
|||
goto host_free;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
host->top_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(host->top_base))
|
||||
host->top_base = NULL;
|
||||
|
||||
ret = mmc_regulator_get_supply(mmc);
|
||||
if (ret)
|
||||
goto host_free;
|
||||
|
|
@ -2143,7 +2308,6 @@ static void msdc_save_reg(struct msdc_host *host)
|
|||
host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
|
||||
host->save_para.iocon = readl(host->base + MSDC_IOCON);
|
||||
host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
|
||||
host->save_para.pad_tune = readl(host->base + tune_reg);
|
||||
host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
|
||||
host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
|
||||
host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
|
||||
|
|
@ -2152,6 +2316,16 @@ static void msdc_save_reg(struct msdc_host *host)
|
|||
host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
|
||||
host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
|
||||
host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
|
||||
if (host->top_base) {
|
||||
host->save_para.emmc_top_control =
|
||||
readl(host->top_base + EMMC_TOP_CONTROL);
|
||||
host->save_para.emmc_top_cmd =
|
||||
readl(host->top_base + EMMC_TOP_CMD);
|
||||
host->save_para.emmc50_pad_ds_tune =
|
||||
readl(host->top_base + EMMC50_PAD_DS_TUNE);
|
||||
} else {
|
||||
host->save_para.pad_tune = readl(host->base + tune_reg);
|
||||
}
|
||||
}
|
||||
|
||||
static void msdc_restore_reg(struct msdc_host *host)
|
||||
|
|
@ -2161,7 +2335,6 @@ static void msdc_restore_reg(struct msdc_host *host)
|
|||
writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
|
||||
writel(host->save_para.iocon, host->base + MSDC_IOCON);
|
||||
writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
|
||||
writel(host->save_para.pad_tune, host->base + tune_reg);
|
||||
writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
|
||||
writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
|
||||
writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
|
||||
|
|
@ -2170,6 +2343,16 @@ static void msdc_restore_reg(struct msdc_host *host)
|
|||
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
|
||||
writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
|
||||
writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
|
||||
if (host->top_base) {
|
||||
writel(host->save_para.emmc_top_control,
|
||||
host->top_base + EMMC_TOP_CONTROL);
|
||||
writel(host->save_para.emmc_top_cmd,
|
||||
host->top_base + EMMC_TOP_CMD);
|
||||
writel(host->save_para.emmc50_pad_ds_tune,
|
||||
host->top_base + EMMC50_PAD_DS_TUNE);
|
||||
} else {
|
||||
writel(host->save_para.pad_tune, host->base + tune_reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int msdc_runtime_suspend(struct device *dev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue