drm/amdgpu: use max_dw in ring_init
Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -215,18 +215,17 @@ int amdgpu_ring_restore(struct amdgpu_ring *ring,
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @ring_size: size of the ring
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* @max_ndw: maximum number of dw for ring alloc
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* @nop: nop packet for this ring
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*
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* Initialize the driver information for the selected ring (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned ring_size, u32 nop, u32 align_mask,
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unsigned max_dw, u32 nop, u32 align_mask,
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struct amdgpu_irq_src *irq_src, unsigned irq_type,
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enum amdgpu_ring_type ring_type)
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{
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u32 rb_bufsz;
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int r;
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if (ring->adev == NULL) {
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@ -283,10 +282,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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return r;
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}
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/* Align ring size */
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rb_bufsz = order_base_2(ring_size / 8);
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ring_size = (1 << (rb_bufsz + 1)) * 4;
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ring->ring_size = ring_size;
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ring->ring_size = roundup_pow_of_two(max_dw * 4 *
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amdgpu_sched_hw_submission);
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ring->align_mask = align_mask;
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ring->nop = nop;
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ring->type = ring_type;
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@ -319,8 +316,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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}
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}
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ring->ptr_mask = (ring->ring_size / 4) - 1;
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ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4,
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amdgpu_sched_hw_submission);
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ring->max_dw = max_dw;
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if (amdgpu_debugfs_ring_init(adev, ring)) {
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DRM_ERROR("Failed to register debugfs file for rings !\n");
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@ -976,7 +976,7 @@ static int cik_sdma_sw_init(void *handle)
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ring = &adev->sdma.instance[i].ring;
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ring->ring_obj = NULL;
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sprintf(ring->name, "sdma%d", i);
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r = amdgpu_ring_init(adev, ring, 256 * 1024,
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r = amdgpu_ring_init(adev, ring, 32 * 1024,
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SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
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&adev->sdma.trap_irq,
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(i == 0) ?
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@ -4414,7 +4414,7 @@ static int gfx_v7_0_sw_init(void *handle)
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ring = &adev->gfx.gfx_ring[i];
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ring->ring_obj = NULL;
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sprintf(ring->name, "gfx");
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r = amdgpu_ring_init(adev, ring, 1024 * 1024,
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r = amdgpu_ring_init(adev, ring, 128 * 1024,
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PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
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&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
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AMDGPU_RING_TYPE_GFX);
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@ -4441,7 +4441,7 @@ static int gfx_v7_0_sw_init(void *handle)
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sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
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/* type-2 packets are deprecated on MEC, use type-3 instead */
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r = amdgpu_ring_init(adev, ring, 1024 * 1024,
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r = amdgpu_ring_init(adev, ring, 128 * 1024,
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PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
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&adev->gfx.eop_irq, irq_type,
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AMDGPU_RING_TYPE_COMPUTE);
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@ -1570,7 +1570,7 @@ static int gfx_v8_0_sw_init(void *handle)
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ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
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}
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r = amdgpu_ring_init(adev, ring, 1024 * 1024,
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r = amdgpu_ring_init(adev, ring, 128 * 1024,
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PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
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&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
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AMDGPU_RING_TYPE_GFX);
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@ -1597,7 +1597,7 @@ static int gfx_v8_0_sw_init(void *handle)
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sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
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/* type-2 packets are deprecated on MEC, use type-3 instead */
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r = amdgpu_ring_init(adev, ring, 1024 * 1024,
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r = amdgpu_ring_init(adev, ring, 128 * 1024,
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PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
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&adev->gfx.eop_irq, irq_type,
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AMDGPU_RING_TYPE_COMPUTE);
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@ -990,7 +990,7 @@ static int sdma_v2_4_sw_init(void *handle)
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ring->ring_obj = NULL;
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ring->use_doorbell = false;
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sprintf(ring->name, "sdma%d", i);
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r = amdgpu_ring_init(adev, ring, 256 * 1024,
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r = amdgpu_ring_init(adev, ring, 32 * 1024,
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SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
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&adev->sdma.trap_irq,
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(i == 0) ?
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@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle)
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ring = &adev->uvd.ring;
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sprintf(ring->name, "uvd");
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r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
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&adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
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return r;
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@ -111,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle)
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ring = &adev->uvd.ring;
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sprintf(ring->name, "uvd");
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r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
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&adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
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return r;
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@ -112,7 +112,7 @@ static int uvd_v6_0_sw_init(void *handle)
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ring = &adev->uvd.ring;
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sprintf(ring->name, "uvd");
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r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
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&adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
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return r;
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@ -201,14 +201,14 @@ static int vce_v2_0_sw_init(void *handle)
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ring = &adev->vce.ring[0];
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sprintf(ring->name, "vce0");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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ring = &adev->vce.ring[1];
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sprintf(ring->name, "vce1");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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@ -381,14 +381,14 @@ static int vce_v3_0_sw_init(void *handle)
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ring = &adev->vce.ring[0];
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sprintf(ring->name, "vce0");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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ring = &adev->vce.ring[1];
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sprintf(ring->name, "vce1");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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