tools headers: Sync kernel ABI headers with tooling headers
Sync up (copy) the following v4.13 kernel headers to the tooling headers: arch/arm/include/uapi/asm/kvm.h: arch/arm64/include/uapi/asm/kvm.h: arch/powerpc/include/uapi/asm/kvm.h: arch/s390/include/uapi/asm/kvm.h: - KVM ABI extensions, which do not affect perf tooling arch/x86/include/asm/cpufeatures.h: arch/x86/include/asm/disabled-features.h: - New PCID CPU feature on Intel CPUs - does not affect tooling. I.e. no real changes were needed to resolve the build warnings, just a plain copy of the latest kernel header version. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: David Ahern <dsahern@gmail.com> Cc: David Carrillo-Cisneros <davidcc@google.com> Cc: Francis Deslauriers <francis.deslauriers@efficios.com> Cc: Geneviève Bastien <gbastien@versatic.net> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Julien Desfossez <jdesfossez@efficios.com> Cc: Martin Liška <mliska@suse.cz> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Milian Wolff <milian.wolff@kdab.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Simon Que <sque@chromium.org> Cc: Stephane Eranian <eranian@google.com> Cc: Taeung Song <treeze.taeung@gmail.com> Cc: Wang Nan <wangnan0@huawei.com> Link: http://lkml.kernel.org/r/20170730095232.4j4xigsoqwufl5hu@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -203,6 +203,14 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
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#define VGIC_LEVEL_INFO_LINE_LEVEL 0
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/* Device Control API on vcpu fd */
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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#define KVM_ARM_VCPU_PMU_V3_IRQ 0
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#define KVM_ARM_VCPU_PMU_V3_INIT 1
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#define KVM_ARM_VCPU_TIMER_CTRL 1
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#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
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#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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@ -232,6 +232,9 @@ struct kvm_arch_memory_slot {
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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#define KVM_ARM_VCPU_PMU_V3_IRQ 0
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#define KVM_ARM_VCPU_PMU_V3_INIT 1
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#define KVM_ARM_VCPU_TIMER_CTRL 1
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#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
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#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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@ -60,6 +60,12 @@ struct kvm_regs {
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#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
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/* flags for kvm_run.flags */
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#define KVM_RUN_PPC_NMI_DISP_MASK (3 << 0)
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#define KVM_RUN_PPC_NMI_DISP_FULLY_RECOV (1 << 0)
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#define KVM_RUN_PPC_NMI_DISP_LIMITED_RECOV (2 << 0)
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#define KVM_RUN_PPC_NMI_DISP_NOT_RECOV (3 << 0)
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/*
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* Feature bits indicate which sections of the sregs struct are valid,
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* both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
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@ -28,6 +28,7 @@
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#define KVM_DEV_FLIC_CLEAR_IO_IRQ 8
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#define KVM_DEV_FLIC_AISM 9
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#define KVM_DEV_FLIC_AIRQ_INJECT 10
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#define KVM_DEV_FLIC_AISM_ALL 11
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/*
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* We can have up to 4*64k pending subchannels + 8 adapter interrupts,
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* as well as up to ASYNC_PF_PER_VCPU*KVM_MAX_VCPUS pfault done interrupts.
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@ -53,6 +54,11 @@ struct kvm_s390_ais_req {
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__u16 mode;
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};
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struct kvm_s390_ais_all {
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__u8 simm;
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__u8 nimm;
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};
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#define KVM_S390_IO_ADAPTER_MASK 1
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#define KVM_S390_IO_ADAPTER_MAP 2
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#define KVM_S390_IO_ADAPTER_UNMAP 3
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@ -70,6 +76,7 @@ struct kvm_s390_io_adapter_req {
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#define KVM_S390_VM_TOD 1
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#define KVM_S390_VM_CRYPTO 2
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#define KVM_S390_VM_CPU_MODEL 3
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#define KVM_S390_VM_MIGRATION 4
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/* kvm attributes for mem_ctrl */
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#define KVM_S390_VM_MEM_ENABLE_CMMA 0
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@ -151,6 +158,11 @@ struct kvm_s390_vm_cpu_subfunc {
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#define KVM_S390_VM_CRYPTO_DISABLE_AES_KW 2
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#define KVM_S390_VM_CRYPTO_DISABLE_DEA_KW 3
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/* kvm attributes for migration mode */
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#define KVM_S390_VM_MIGRATION_STOP 0
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#define KVM_S390_VM_MIGRATION_START 1
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#define KVM_S390_VM_MIGRATION_STATUS 2
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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/* general purpose regs for s390 */
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@ -196,6 +196,7 @@
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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@ -286,6 +287,7 @@
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#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
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#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
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#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
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#define X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE (15*32+15) /* Virtual VMLOAD VMSAVE */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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@ -21,11 +21,13 @@
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# define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31))
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# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31))
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# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31))
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# define DISABLE_PCID 0
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#else
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# define DISABLE_VME 0
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# define DISABLE_K6_MTRR 0
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# define DISABLE_CYRIX_ARR 0
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# define DISABLE_CENTAUR_MCR 0
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# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31))
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#endif /* CONFIG_X86_64 */
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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@ -49,7 +51,7 @@
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#define DISABLED_MASK1 0
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#define DISABLED_MASK2 0
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#define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR)
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#define DISABLED_MASK4 0
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#define DISABLED_MASK4 (DISABLE_PCID)
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#define DISABLED_MASK5 0
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#define DISABLED_MASK6 0
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#define DISABLED_MASK7 0
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