MIPS: SGI-IP27: clean up bridge access and header files
Introduced bridge_read/bridge_write/bridge_set/bridge_clr for accessing bridge register and get rid of volatile declarations. Also removed all typedefs from arch/mips/include/asm/pci/bridge.h and cleaned up language in arch/mips/pci/ops-bridge.c Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Thomas Bogendoerfer
Paul Burton
parent
db0e7d4e42
commit
a44d924c81
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@ -45,18 +45,21 @@
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#ifndef __ASSEMBLY__
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/*
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* All accesses to bridge hardware registers must be done
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* using 32-bit loads and stores.
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*/
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typedef u32 bridgereg_t;
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#define ATE_V 0x01
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#define ATE_CO 0x02
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#define ATE_PREC 0x04
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#define ATE_PREF 0x08
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#define ATE_BAR 0x10
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typedef u64 bridge_ate_t;
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#define ATE_PFNSHIFT 12
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#define ATE_TIDSHIFT 8
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#define ATE_RMFSHIFT 48
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/* pointers to bridge ATEs
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* are always "pointer to volatile"
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*/
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typedef volatile bridge_ate_t *bridge_ate_p;
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#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
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((xid)<<ATE_TIDSHIFT) | \
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(attr))
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#define BRIDGE_INTERNAL_ATES 128
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/*
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* It is generally preferred that hardware registers on the bridge
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@ -65,7 +68,7 @@ typedef volatile bridge_ate_t *bridge_ate_p;
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* Generated from Bridge spec dated 04oct95
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*/
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typedef volatile struct bridge_s {
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struct bridge_regs {
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/* Local Registers 0x000000-0x00FFFF */
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/* standard widget configuration 0x000000-0x000057 */
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@ -86,105 +89,105 @@ typedef volatile struct bridge_s {
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#define b_wid_tflush b_widget.w_tflush
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/* bridge-specific widget configuration 0x000058-0x00007F */
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bridgereg_t _pad_000058;
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bridgereg_t b_wid_aux_err; /* 0x00005C */
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bridgereg_t _pad_000060;
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bridgereg_t b_wid_resp_upper; /* 0x000064 */
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bridgereg_t _pad_000068;
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bridgereg_t b_wid_resp_lower; /* 0x00006C */
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bridgereg_t _pad_000070;
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bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
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bridgereg_t _pad_000078[2];
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u32 _pad_000058;
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u32 b_wid_aux_err; /* 0x00005C */
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u32 _pad_000060;
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u32 b_wid_resp_upper; /* 0x000064 */
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u32 _pad_000068;
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u32 b_wid_resp_lower; /* 0x00006C */
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u32 _pad_000070;
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u32 b_wid_tst_pin_ctrl; /* 0x000074 */
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u32 _pad_000078[2];
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/* PMU & Map 0x000080-0x00008F */
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bridgereg_t _pad_000080;
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bridgereg_t b_dir_map; /* 0x000084 */
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bridgereg_t _pad_000088[2];
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u32 _pad_000080;
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u32 b_dir_map; /* 0x000084 */
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u32 _pad_000088[2];
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/* SSRAM 0x000090-0x00009F */
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bridgereg_t _pad_000090;
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bridgereg_t b_ram_perr; /* 0x000094 */
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bridgereg_t _pad_000098[2];
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u32 _pad_000090;
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u32 b_ram_perr; /* 0x000094 */
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u32 _pad_000098[2];
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/* Arbitration 0x0000A0-0x0000AF */
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bridgereg_t _pad_0000A0;
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bridgereg_t b_arb; /* 0x0000A4 */
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bridgereg_t _pad_0000A8[2];
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u32 _pad_0000A0;
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u32 b_arb; /* 0x0000A4 */
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u32 _pad_0000A8[2];
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/* Number In A Can 0x0000B0-0x0000BF */
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bridgereg_t _pad_0000B0;
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bridgereg_t b_nic; /* 0x0000B4 */
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bridgereg_t _pad_0000B8[2];
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u32 _pad_0000B0;
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u32 b_nic; /* 0x0000B4 */
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u32 _pad_0000B8[2];
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/* PCI/GIO 0x0000C0-0x0000FF */
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bridgereg_t _pad_0000C0;
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bridgereg_t b_bus_timeout; /* 0x0000C4 */
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u32 _pad_0000C0;
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u32 b_bus_timeout; /* 0x0000C4 */
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#define b_pci_bus_timeout b_bus_timeout
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bridgereg_t _pad_0000C8;
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bridgereg_t b_pci_cfg; /* 0x0000CC */
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bridgereg_t _pad_0000D0;
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bridgereg_t b_pci_err_upper; /* 0x0000D4 */
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bridgereg_t _pad_0000D8;
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bridgereg_t b_pci_err_lower; /* 0x0000DC */
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bridgereg_t _pad_0000E0[8];
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u32 _pad_0000C8;
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u32 b_pci_cfg; /* 0x0000CC */
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u32 _pad_0000D0;
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u32 b_pci_err_upper; /* 0x0000D4 */
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u32 _pad_0000D8;
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u32 b_pci_err_lower; /* 0x0000DC */
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u32 _pad_0000E0[8];
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#define b_gio_err_lower b_pci_err_lower
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#define b_gio_err_upper b_pci_err_upper
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/* Interrupt 0x000100-0x0001FF */
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bridgereg_t _pad_000100;
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bridgereg_t b_int_status; /* 0x000104 */
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bridgereg_t _pad_000108;
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bridgereg_t b_int_enable; /* 0x00010C */
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bridgereg_t _pad_000110;
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bridgereg_t b_int_rst_stat; /* 0x000114 */
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bridgereg_t _pad_000118;
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bridgereg_t b_int_mode; /* 0x00011C */
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bridgereg_t _pad_000120;
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bridgereg_t b_int_device; /* 0x000124 */
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bridgereg_t _pad_000128;
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bridgereg_t b_int_host_err; /* 0x00012C */
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u32 _pad_000100;
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u32 b_int_status; /* 0x000104 */
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u32 _pad_000108;
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u32 b_int_enable; /* 0x00010C */
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u32 _pad_000110;
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u32 b_int_rst_stat; /* 0x000114 */
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u32 _pad_000118;
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u32 b_int_mode; /* 0x00011C */
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u32 _pad_000120;
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u32 b_int_device; /* 0x000124 */
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u32 _pad_000128;
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u32 b_int_host_err; /* 0x00012C */
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struct {
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bridgereg_t __pad; /* 0x0001{30,,,68} */
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bridgereg_t addr; /* 0x0001{34,,,6C} */
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u32 __pad; /* 0x0001{30,,,68} */
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u32 addr; /* 0x0001{34,,,6C} */
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} b_int_addr[8]; /* 0x000130 */
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bridgereg_t _pad_000170[36];
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u32 _pad_000170[36];
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/* Device 0x000200-0x0003FF */
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struct {
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bridgereg_t __pad; /* 0x0002{00,,,38} */
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bridgereg_t reg; /* 0x0002{04,,,3C} */
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u32 __pad; /* 0x0002{00,,,38} */
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u32 reg; /* 0x0002{04,,,3C} */
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} b_device[8]; /* 0x000200 */
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struct {
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bridgereg_t __pad; /* 0x0002{40,,,78} */
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bridgereg_t reg; /* 0x0002{44,,,7C} */
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u32 __pad; /* 0x0002{40,,,78} */
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u32 reg; /* 0x0002{44,,,7C} */
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} b_wr_req_buf[8]; /* 0x000240 */
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struct {
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bridgereg_t __pad; /* 0x0002{80,,,88} */
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bridgereg_t reg; /* 0x0002{84,,,8C} */
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u32 __pad; /* 0x0002{80,,,88} */
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u32 reg; /* 0x0002{84,,,8C} */
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} b_rrb_map[2]; /* 0x000280 */
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#define b_even_resp b_rrb_map[0].reg /* 0x000284 */
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#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
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bridgereg_t _pad_000290;
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bridgereg_t b_resp_status; /* 0x000294 */
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bridgereg_t _pad_000298;
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bridgereg_t b_resp_clear; /* 0x00029C */
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u32 _pad_000290;
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u32 b_resp_status; /* 0x000294 */
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u32 _pad_000298;
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u32 b_resp_clear; /* 0x00029C */
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bridgereg_t _pad_0002A0[24];
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u32 _pad_0002A0[24];
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char _pad_000300[0x10000 - 0x000300];
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/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
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union {
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bridge_ate_t wr; /* write-only */
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u64 wr; /* write-only */
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struct {
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bridgereg_t _p_pad;
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bridgereg_t rd; /* read-only */
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u32 _p_pad;
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u32 rd; /* read-only */
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} hi;
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} b_int_ate_ram[128];
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@ -192,8 +195,8 @@ typedef volatile struct bridge_s {
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/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
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struct {
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bridgereg_t _p_pad;
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bridgereg_t rd; /* read-only */
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u32 _p_pad;
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u32 rd; /* read-only */
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} b_int_ate_ram_lo[128];
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char _pad_011400[0x20000 - 0x011400];
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@ -212,7 +215,7 @@ typedef volatile struct bridge_s {
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} f[8];
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} b_type0_cfg_dev[8]; /* 0x020000 */
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/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
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/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
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union { /* make all access sizes available. */
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u8 c[0x1000 / 1];
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u16 s[0x1000 / 2];
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@ -233,7 +236,7 @@ typedef volatile struct bridge_s {
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u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
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/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
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bridge_ate_t b_ext_ate_ram[0x10000];
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u64 b_ext_ate_ram[0x10000];
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/* Reserved 0x100000-0x1FFFFF */
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char _pad_100000[0x200000-0x100000];
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@ -259,13 +262,13 @@ typedef volatile struct bridge_s {
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u32 l[0x400000 / 4]; /* read-only */
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u64 d[0x400000 / 8]; /* read-only */
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} b_external_flash; /* 0xC00000 */
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} bridge_t;
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};
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/*
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* Field formats for Error Command Word and Auxiliary Error Command Word
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* of bridge.
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*/
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typedef struct bridge_err_cmdword_s {
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struct bridge_err_cmdword {
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union {
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u32 cmd_word;
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struct {
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@ -282,7 +285,7 @@ typedef struct bridge_err_cmdword_s {
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rsvd:8;
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} berr_st;
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} berr_un;
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} bridge_err_cmdword_t;
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};
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#define berr_field berr_un.berr_st
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#endif /* !__ASSEMBLY__ */
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@ -290,7 +293,7 @@ typedef struct bridge_err_cmdword_s {
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/*
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* The values of these macros can and should be crosschecked
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* regularly against the offsets of the like-named fields
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* within the "bridge_t" structure above.
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* within the bridge_regs structure above.
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*/
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/* Byte offset macros for Bridge internal registers */
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@ -797,46 +800,12 @@ typedef struct bridge_err_cmdword_s {
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#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
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#define PCI64_ATTR_RMF_SHFT 48
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#ifndef __ASSEMBLY__
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/* Address translation entry for mapped pci32 accesses */
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typedef union ate_u {
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u64 ent;
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struct ate_s {
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u64 rmf:16;
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u64 addr:36;
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u64 targ:4;
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u64 reserved:3;
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u64 barrier:1;
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u64 prefetch:1;
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u64 precise:1;
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u64 coherent:1;
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u64 valid:1;
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} field;
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} ate_t;
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#endif /* !__ASSEMBLY__ */
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#define ATE_V 0x01
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#define ATE_CO 0x02
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#define ATE_PREC 0x04
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#define ATE_PREF 0x08
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#define ATE_BAR 0x10
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#define ATE_PFNSHIFT 12
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#define ATE_TIDSHIFT 8
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#define ATE_RMFSHIFT 48
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#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
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((xid)<<ATE_TIDSHIFT) | \
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(attr)
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#define BRIDGE_INTERNAL_ATES 128
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struct bridge_controller {
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struct pci_controller pc;
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struct resource mem;
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struct resource io;
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struct resource busn;
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bridge_t *base;
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struct bridge_regs *base;
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nasid_t nasid;
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unsigned int widget_id;
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unsigned int irq_cpu;
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@ -847,6 +816,13 @@ struct bridge_controller {
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#define BRIDGE_CONTROLLER(bus) \
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((struct bridge_controller *)((bus)->sysdata))
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#define bridge_read(bc, reg) __raw_readl(&bc->base->reg)
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#define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg)
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#define bridge_set(bc, reg, val) \
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__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
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#define bridge_clr(bc, reg, val) \
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__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
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extern void register_bridge_irq(unsigned int irq);
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extern int request_bridge_irq(struct bridge_controller *bc);
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@ -134,11 +134,6 @@
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#define CALIAS_BASE CAC_BASE
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#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
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((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
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#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
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/* Turn on sable logging for the processors whose bits are set. */
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@ -44,7 +44,7 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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struct bridge_regs *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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volatile void *addr;
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@ -56,11 +56,11 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucking fucked beyond belief ... Don't even give the
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* IOC3 is broken beyond belief ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto oh_my_gawd;
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goto is_ioc3;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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@ -73,21 +73,16 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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oh_my_gawd:
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is_ioc3:
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/*
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* IOC3 is fucking fucked beyond belief ... Don't even give the
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* generic PCI code a chance to look at the wrong register.
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* IOC3 special handling
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = emulate_ioc3_cfg(where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* IOC3 is fucking fucked beyond belief ... Don't try to access
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* anything but 32-bit words ...
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*/
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *) addr))
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@ -104,7 +99,7 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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bridge_t *bridge = bc->base;
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struct bridge_regs *bridge = bc->base;
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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@ -112,19 +107,19 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
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u32 cf, shift, mask;
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int res;
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bridge->b_pci_cfg = (busno << 16) | (slot << 11);
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bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *) addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* IOC3 is broken beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to look at it for real ...
|
||||
*/
|
||||
if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
|
||||
goto oh_my_gawd;
|
||||
goto is_ioc3;
|
||||
|
||||
bridge->b_pci_cfg = (busno << 16) | (slot << 11);
|
||||
bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
|
||||
addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
|
||||
|
||||
if (size == 1)
|
||||
|
|
@ -136,22 +131,17 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
|
|||
|
||||
return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||||
|
||||
oh_my_gawd:
|
||||
is_ioc3:
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to look at the wrong register.
|
||||
* IOC3 special handling
|
||||
*/
|
||||
if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
|
||||
*value = emulate_ioc3_cfg(where, size);
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't try to access
|
||||
* anything but 32-bit words ...
|
||||
*/
|
||||
bridge->b_pci_cfg = (busno << 16) | (slot << 11);
|
||||
bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
|
||||
addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
|
||||
|
||||
if (get_dbe(cf, (u32 *) addr))
|
||||
|
|
@ -177,7 +167,7 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
int where, int size, u32 value)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
|
||||
bridge_t *bridge = bc->base;
|
||||
struct bridge_regs *bridge = bc->base;
|
||||
int slot = PCI_SLOT(devfn);
|
||||
int fn = PCI_FUNC(devfn);
|
||||
volatile void *addr;
|
||||
|
|
@ -189,11 +179,11 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* IOC3 is broken beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to look at it for real ...
|
||||
*/
|
||||
if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
|
||||
goto oh_my_gawd;
|
||||
goto is_ioc3;
|
||||
|
||||
addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
|
||||
|
||||
|
|
@ -210,19 +200,14 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
oh_my_gawd:
|
||||
is_ioc3:
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to touch the wrong register.
|
||||
* IOC3 special handling
|
||||
*/
|
||||
if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't try to access
|
||||
* anything but 32-bit words ...
|
||||
*/
|
||||
addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
|
||||
|
||||
if (get_dbe(cf, (u32 *) addr))
|
||||
|
|
@ -243,7 +228,7 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
int where, int size, u32 value)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
|
||||
bridge_t *bridge = bc->base;
|
||||
struct bridge_regs *bridge = bc->base;
|
||||
int slot = PCI_SLOT(devfn);
|
||||
int fn = PCI_FUNC(devfn);
|
||||
int busno = bus->number;
|
||||
|
|
@ -251,17 +236,17 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
u32 cf, shift, mask, smask;
|
||||
int res;
|
||||
|
||||
bridge->b_pci_cfg = (busno << 16) | (slot << 11);
|
||||
bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
|
||||
addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
|
||||
if (get_dbe(cf, (u32 *) addr))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* IOC3 is broken beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to look at it for real ...
|
||||
*/
|
||||
if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
|
||||
goto oh_my_gawd;
|
||||
goto is_ioc3;
|
||||
|
||||
addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
|
||||
|
||||
|
|
@ -278,19 +263,14 @@ static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
|
|||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
oh_my_gawd:
|
||||
is_ioc3:
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't even give the
|
||||
* generic PCI code a chance to touch the wrong register.
|
||||
* IOC3 special handling
|
||||
*/
|
||||
if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
|
||||
/*
|
||||
* IOC3 is fucking fucked beyond belief ... Don't try to access
|
||||
* anything but 32-bit words ...
|
||||
*/
|
||||
addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
|
||||
|
||||
if (get_dbe(cf, (u32 *) addr))
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
|
|||
unsigned long offset = NODE_OFFSET(nasid);
|
||||
struct bridge_controller *bc;
|
||||
static int num_bridges = 0;
|
||||
bridge_t *bridge;
|
||||
int slot;
|
||||
|
||||
pci_set_flags(PCI_PROBE_ONLY);
|
||||
|
|
@ -87,45 +86,43 @@ int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
|
|||
/*
|
||||
* point to this bridge
|
||||
*/
|
||||
bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
|
||||
bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id);
|
||||
|
||||
/*
|
||||
* Clear all pending interrupts.
|
||||
*/
|
||||
bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
|
||||
bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
|
||||
|
||||
/*
|
||||
* Until otherwise set up, assume all interrupts are from slot 0
|
||||
*/
|
||||
bridge->b_int_device = 0x0;
|
||||
bridge_write(bc, b_int_device, 0x0);
|
||||
|
||||
/*
|
||||
* swap pio's to pci mem and io space (big windows)
|
||||
*/
|
||||
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
|
||||
BRIDGE_CTRL_MEM_SWAP;
|
||||
bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP |
|
||||
BRIDGE_CTRL_MEM_SWAP);
|
||||
#ifdef CONFIG_PAGE_SIZE_4KB
|
||||
bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
|
||||
bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
|
||||
#else /* 16kB or larger */
|
||||
bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
|
||||
bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Hmm... IRIX sets additional bits in the address which
|
||||
* are documented as reserved in the bridge docs.
|
||||
*/
|
||||
bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
|
||||
bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/
|
||||
bridge->b_dir_map = (masterwid << 20); /* DMA */
|
||||
bridge->b_int_enable = 0;
|
||||
bridge_write(bc, b_wid_int_upper, 0x8000 | (masterwid << 16));
|
||||
bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/
|
||||
bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */
|
||||
bridge_write(bc, b_int_enable, 0);
|
||||
|
||||
for (slot = 0; slot < 8; slot ++) {
|
||||
bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
|
||||
bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
|
||||
bc->pci_int[slot] = -1;
|
||||
}
|
||||
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
|
||||
|
||||
bc->base = bridge;
|
||||
bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
|
||||
|
||||
register_pci_controller(&bc->pc);
|
||||
|
||||
|
|
@ -206,7 +203,7 @@ phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
|
|||
static inline void pci_disable_swapping(struct pci_dev *dev)
|
||||
{
|
||||
struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
|
||||
bridge_t *bridge = bc->base;
|
||||
struct bridge_regs *bridge = bc->base;
|
||||
int slot = PCI_SLOT(dev->devfn);
|
||||
|
||||
/* Turn off byte swapping */
|
||||
|
|
|
|||
|
|
@ -136,14 +136,12 @@ static int intr_disconnect_level(int cpu, int bit)
|
|||
static unsigned int startup_bridge_irq(struct irq_data *d)
|
||||
{
|
||||
struct bridge_controller *bc;
|
||||
bridgereg_t device;
|
||||
bridge_t *bridge;
|
||||
int pin, swlevel;
|
||||
cpuid_t cpu;
|
||||
u64 device;
|
||||
|
||||
pin = SLOT_FROM_PCI_IRQ(d->irq);
|
||||
bc = IRQ_TO_BRIDGE(d->irq);
|
||||
bridge = bc->base;
|
||||
|
||||
pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
|
||||
/*
|
||||
|
|
@ -151,9 +149,10 @@ static unsigned int startup_bridge_irq(struct irq_data *d)
|
|||
* of INT_PEND0 are taken
|
||||
*/
|
||||
swlevel = find_level(&cpu, d->irq);
|
||||
bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
|
||||
bridge->b_int_enable |= (1 << pin);
|
||||
bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
|
||||
bridge_write(bc, b_int_addr[pin].addr,
|
||||
(0x20000 | swlevel | (bc->nasid << 8)));
|
||||
bridge_set(bc, b_int_enable, (1 << pin));
|
||||
bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
|
||||
|
||||
/*
|
||||
* Enable sending of an interrupt clear packt to the hub on a high to
|
||||
|
|
@ -162,18 +161,18 @@ static unsigned int startup_bridge_irq(struct irq_data *d)
|
|||
* IRIX sets additional bits in the address which are documented as
|
||||
* reserved in the bridge docs.
|
||||
*/
|
||||
bridge->b_int_mode |= (1UL << pin);
|
||||
bridge_set(bc, b_int_mode, (1UL << pin));
|
||||
|
||||
/*
|
||||
* We assume the bridge to have a 1:1 mapping between devices
|
||||
* (slots) and intr pins.
|
||||
*/
|
||||
device = bridge->b_int_device;
|
||||
device = bridge_read(bc, b_int_device);
|
||||
device &= ~(7 << (pin*3));
|
||||
device |= (pin << (pin*3));
|
||||
bridge->b_int_device = device;
|
||||
bridge_write(bc, b_int_device, device);
|
||||
|
||||
bridge->b_wid_tflush;
|
||||
bridge_read(bc, b_wid_tflush);
|
||||
|
||||
intr_connect_level(cpu, swlevel);
|
||||
|
||||
|
|
@ -184,7 +183,6 @@ static unsigned int startup_bridge_irq(struct irq_data *d)
|
|||
static void shutdown_bridge_irq(struct irq_data *d)
|
||||
{
|
||||
struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
|
||||
bridge_t *bridge = bc->base;
|
||||
int pin, swlevel;
|
||||
cpuid_t cpu;
|
||||
|
||||
|
|
@ -198,8 +196,8 @@ static void shutdown_bridge_irq(struct irq_data *d)
|
|||
swlevel = find_level(&cpu, d->irq);
|
||||
intr_disconnect_level(cpu, swlevel);
|
||||
|
||||
bridge->b_int_enable &= ~(1 << pin);
|
||||
bridge->b_wid_tflush;
|
||||
bridge_clr(bc, b_int_enable, (1 << pin));
|
||||
bridge_read(bc, b_wid_tflush);
|
||||
}
|
||||
|
||||
static inline void enable_bridge_irq(struct irq_data *d)
|
||||
|
|
|
|||
Loading…
Reference in New Issue