x86/hyper-v: Do some housekeeping in hyperv-tlfs.h
hyperv-tlfs.h is a bit messy: CPUID feature bits are not always sorted, it's hard to get which CPUID they belong to, some items are duplicated (e.g. HV_X64_MSR_CRASH_CTL_NOTIFY/HV_CRASH_CTL_CRASH_NOTIFY). Do some housekeeping work. While on it, replace all (1 << X) with BIT(X) macro. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Vitaly Kuznetsov
Paolo Bonzini
parent
ec08449172
commit
a4987defc1
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@ -30,158 +30,151 @@
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/*
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* Feature identification. EAX indicates which features are available
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* to the partition based upon the current partition privileges.
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* These are HYPERV_CPUID_FEATURES.EAX bits.
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*/
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/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
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#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
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#define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0)
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/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
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#define HV_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
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/* Partition reference TSC MSR is available */
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#define HV_MSR_REFERENCE_TSC_AVAILABLE (1 << 9)
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/* Partition Guest IDLE MSR is available */
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#define HV_X64_MSR_GUEST_IDLE_AVAILABLE (1 << 10)
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/* A partition's reference time stamp counter (TSC) page */
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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/*
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* There is a single feature flag that signifies if the partition has access
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* to MSRs with local APIC and TSC frequencies.
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*/
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#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11)
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/* AccessReenlightenmentControls privilege */
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#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13)
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#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)
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/*
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* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
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* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
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*/
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#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
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#define HV_X64_MSR_SYNIC_AVAILABLE BIT(2)
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/*
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* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
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* HV_X64_MSR_STIMER3_COUNT) available
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*/
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#define HV_MSR_SYNTIMER_AVAILABLE (1 << 3)
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#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)
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/*
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* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
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* are available
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*/
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#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
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#define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4)
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/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
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#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
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#define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5)
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/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
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#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
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#define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6)
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/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
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#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
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/*
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* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
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* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
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* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
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*/
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#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
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/* Frequency MSRs available */
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#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8)
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/* Crash MSR available */
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#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
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/* stimer Direct Mode is available */
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#define HV_STIMER_DIRECT_MODE_AVAILABLE (1 << 19)
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#define HV_X64_MSR_RESET_AVAILABLE BIT(7)
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/*
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* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
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* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
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* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
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*/
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#define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8)
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/* Partition reference TSC MSR is available */
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#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)
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/* Partition Guest IDLE MSR is available */
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#define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10)
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/*
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* There is a single feature flag that signifies if the partition has access
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* to MSRs with local APIC and TSC frequencies.
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*/
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#define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11)
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/* AccessReenlightenmentControls privilege */
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#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13)
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/*
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* Feature identification: EBX indicates which flags were specified at
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* partition creation. The format is the same as the partition creation
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* flag structure defined in section Partition Creation Flags.
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* Feature identification: indicates which flags were specified at partition
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* creation. The format is the same as the partition creation flag structure
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* defined in section Partition Creation Flags.
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* These are HYPERV_CPUID_FEATURES.EBX bits.
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*/
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#define HV_X64_CREATE_PARTITIONS (1 << 0)
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#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
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#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
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#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
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#define HV_X64_POST_MESSAGES (1 << 4)
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#define HV_X64_SIGNAL_EVENTS (1 << 5)
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#define HV_X64_CREATE_PORT (1 << 6)
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#define HV_X64_CONNECT_PORT (1 << 7)
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#define HV_X64_ACCESS_STATS (1 << 8)
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#define HV_X64_DEBUGGING (1 << 11)
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#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
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#define HV_X64_CONFIGURE_PROFILER (1 << 13)
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#define HV_X64_CREATE_PARTITIONS BIT(0)
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#define HV_X64_ACCESS_PARTITION_ID BIT(1)
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#define HV_X64_ACCESS_MEMORY_POOL BIT(2)
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#define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3)
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#define HV_X64_POST_MESSAGES BIT(4)
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#define HV_X64_SIGNAL_EVENTS BIT(5)
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#define HV_X64_CREATE_PORT BIT(6)
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#define HV_X64_CONNECT_PORT BIT(7)
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#define HV_X64_ACCESS_STATS BIT(8)
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#define HV_X64_DEBUGGING BIT(11)
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#define HV_X64_CPU_POWER_MANAGEMENT BIT(12)
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#define HV_X64_CONFIGURE_PROFILER BIT(13)
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/*
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* Feature identification. EDX indicates which miscellaneous features
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* are available to the partition.
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* These are HYPERV_CPUID_FEATURES.EDX bits.
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*/
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/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
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#define HV_X64_MWAIT_AVAILABLE (1 << 0)
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#define HV_X64_MWAIT_AVAILABLE BIT(0)
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/* Guest debugging support is available */
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#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
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#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1)
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/* Performance Monitor support is available*/
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#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
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#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2)
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/* Support for physical CPU dynamic partitioning events is available*/
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#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
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#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3)
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/*
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* Support for passing hypercall input parameter block via XMM
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* registers is available
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*/
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#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
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#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4)
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/* Support for a virtual guest idle state is available */
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#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
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/* Guest crash data handler available */
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#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
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#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5)
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/* Frequency MSRs available */
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#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8)
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/* Crash MSR available */
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#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10)
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/* stimer Direct Mode is available */
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#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19)
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/*
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* Implementation recommendations. Indicates which behaviors the hypervisor
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* recommends the OS implement for optimal performance.
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* These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
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*/
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/*
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* Recommend using hypercall for address space switches rather
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* than MOV to CR3 instruction
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*/
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#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0)
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/*
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* Recommend using hypercall for address space switches rather
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* than MOV to CR3 instruction
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*/
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#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0)
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/* Recommend using hypercall for local TLB flushes rather
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* than INVLPG or MOV to CR3 instructions */
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#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
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#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1)
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/*
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* Recommend using hypercall for remote TLB flushes rather
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* than inter-processor interrupts
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*/
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#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
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#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2)
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/*
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* Recommend using MSRs for accessing APIC registers
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* EOI, ICR and TPR rather than their memory-mapped counterparts
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*/
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#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
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#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3)
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/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
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#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
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#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4)
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/*
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* Recommend using relaxed timing for this partition. If used,
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* the VM should disable any watchdog timeouts that rely on the
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* timely delivery of external interrupts
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*/
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#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
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#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5)
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/*
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* Recommend not using Auto End-Of-Interrupt feature
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*/
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#define HV_DEPRECATING_AEOI_RECOMMENDED (1 << 9)
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#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9)
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/*
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* Recommend using cluster IPI hypercalls.
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*/
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#define HV_X64_CLUSTER_IPI_RECOMMENDED (1 << 10)
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#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10)
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/* Recommend using the newer ExProcessorMasks interface */
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#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11)
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#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11)
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/* Recommend using enlightened VMCS */
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#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED (1 << 14)
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#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14)
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/*
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* Crash notification flags.
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*/
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#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
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#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
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/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
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#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
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#define HV_X64_NESTED_MSR_BITMAP BIT(19)
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/* Hyper-V specific model specific registers (MSRs) */
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/* MSR used to identify the guest OS. */
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000
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@ -201,6 +194,9 @@
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/* MSR used to read the per-partition time reference counter */
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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/* A partition's reference time stamp counter (TSC) page */
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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/* MSR used to retrieve the TSC frequency */
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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@ -258,9 +254,11 @@
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#define HV_X64_MSR_CRASH_P3 0x40000103
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#define HV_X64_MSR_CRASH_P4 0x40000104
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#define HV_X64_MSR_CRASH_CTL 0x40000105
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#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
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#define HV_X64_MSR_CRASH_PARAMS \
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(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
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/* TSC emulation after migration */
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#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
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#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
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#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
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/*
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* Declare the MSR used to setup pages used to communicate with the hypervisor.
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@ -311,13 +309,6 @@ struct ms_hyperv_tsc_page {
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#define HV_LINUX_VENDOR_ID 0x8100
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/* TSC emulation after migration */
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#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
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/* Nested features (CPUID 0x4000000A) EAX */
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#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
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#define HV_X64_NESTED_MSR_BITMAP BIT(19)
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struct hv_reenlightenment_control {
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__u64 vector:8;
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__u64 reserved1:8;
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@ -326,9 +317,6 @@ struct hv_reenlightenment_control {
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__u64 target_vp:32;
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} __packed;
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#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
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#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
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struct hv_tsc_emulation_control {
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__u64 enabled:1;
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__u64 reserved:63;
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@ -344,6 +332,14 @@ struct hv_tsc_emulation_status {
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#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
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(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
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/*
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* Crash notification (HV_X64_MSR_CRASH_CTL) flags.
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*/
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#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
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#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
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#define HV_X64_MSR_CRASH_PARAMS \
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(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
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#define HV_IPI_LOW_VECTOR 0x10
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#define HV_IPI_HIGH_VECTOR 0xff
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@ -809,9 +809,9 @@ static int kvm_hv_msr_set_crash_ctl(struct kvm_vcpu *vcpu, u64 data, bool host)
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struct kvm_hv *hv = &vcpu->kvm->arch.hyperv;
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if (host)
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hv->hv_crash_ctl = data & HV_X64_MSR_CRASH_CTL_NOTIFY;
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hv->hv_crash_ctl = data & HV_CRASH_CTL_CRASH_NOTIFY;
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if (!host && (data & HV_X64_MSR_CRASH_CTL_NOTIFY)) {
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if (!host && (data & HV_CRASH_CTL_CRASH_NOTIFY)) {
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vcpu_debug(vcpu, "hv crash (0x%llx 0x%llx 0x%llx 0x%llx 0x%llx)\n",
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hv->hv_crash_param[0],
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