net: aquantia: Introduce support for new firmware on AQC cards
This defines fw2x operations table and corresponding methods. Some of the functions are being shared with 1.x firmware Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -39,4 +39,5 @@ atlantic-objs := aq_main.o \
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hw_atl/hw_atl_a0.o \
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hw_atl/hw_atl_b0.o \
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hw_atl/hw_atl_utils.o \
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hw_atl/hw_atl_utils_fw2x.o \
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hw_atl/hw_atl_llh.o
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@ -42,7 +42,6 @@ struct aq_hw_caps_s {
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u8 rx_rings;
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bool flow_control;
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bool is_64_dma;
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u32 fw_ver_expected;
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};
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struct aq_hw_link_status_s {
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@ -32,6 +32,8 @@
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#define HW_ATL_MPI_SPEED_SHIFT 16U
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#define HW_ATL_FW_VER_1X 0x01050006U
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#define HW_ATL_FW_VER_2X 0x02000000U
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#define HW_ATL_FW_VER_3X 0x03000000U
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static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
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@ -46,6 +48,12 @@ int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
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if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, self->fw_ver_actual) == 0)
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*fw_ops = &aq_fw_1x_ops;
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else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_2X,
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self->fw_ver_actual) == 0)
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*fw_ops = &aq_fw_2x_ops;
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else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_3X,
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self->fw_ver_actual) == 0)
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*fw_ops = &aq_fw_2x_ops;
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else {
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aq_pr_err("Bad FW version detected: %x\n",
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self->fw_ver_actual);
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@ -56,8 +64,8 @@ int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
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return err;
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}
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static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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u32 *p, u32 cnt)
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int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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u32 *p, u32 cnt)
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{
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int err = 0;
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@ -163,7 +163,7 @@ struct __packed hw_aq_atl_utils_mbox {
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
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#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
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self->chip_features)
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self->chip_features)
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enum hal_atl_utils_fw_state_e {
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MPI_DEINIT = 0,
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@ -180,6 +180,64 @@ enum hal_atl_utils_fw_state_e {
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#define HAL_ATLANTIC_RATE_100M BIT(5)
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#define HAL_ATLANTIC_RATE_INVALID BIT(6)
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enum hw_atl_fw2x_rate {
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FW2X_RATE_100M = 0x20,
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FW2X_RATE_1G = 0x100,
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FW2X_RATE_2G5 = 0x200,
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FW2X_RATE_5G = 0x400,
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FW2X_RATE_10G = 0x800,
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};
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enum hw_atl_fw2x_caps_lo {
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CAPS_LO_10BASET_HD = 0x00,
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CAPS_LO_10BASET_FD,
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CAPS_LO_100BASETX_HD,
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CAPS_LO_100BASET4_HD,
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CAPS_LO_100BASET2_HD,
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CAPS_LO_100BASETX_FD,
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CAPS_LO_100BASET2_FD,
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CAPS_LO_1000BASET_HD,
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CAPS_LO_1000BASET_FD,
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CAPS_LO_2P5GBASET_FD,
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CAPS_LO_5GBASET_FD,
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CAPS_LO_10GBASET_FD,
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};
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enum hw_atl_fw2x_caps_hi {
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CAPS_HI_RESERVED1 = 0x00,
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CAPS_HI_10BASET_EEE,
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CAPS_HI_RESERVED2,
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CAPS_HI_PAUSE,
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CAPS_HI_ASYMMETRIC_PAUSE,
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CAPS_HI_100BASETX_EEE,
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CAPS_HI_RESERVED3,
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CAPS_HI_RESERVED4,
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CAPS_HI_1000BASET_FD_EEE,
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CAPS_HI_2P5GBASET_FD_EEE,
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CAPS_HI_5GBASET_FD_EEE,
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CAPS_HI_10GBASET_FD_EEE,
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CAPS_HI_RESERVED5,
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CAPS_HI_RESERVED6,
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CAPS_HI_RESERVED7,
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CAPS_HI_RESERVED8,
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CAPS_HI_RESERVED9,
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CAPS_HI_CABLE_DIAG,
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CAPS_HI_TEMPERATURE,
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CAPS_HI_DOWNSHIFT,
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CAPS_HI_PTP_AVB_EN,
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CAPS_HI_MEDIA_DETECT,
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CAPS_HI_LINK_DROP,
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CAPS_HI_SLEEP_PROXY,
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CAPS_HI_WOL,
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CAPS_HI_MAC_STOP,
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CAPS_HI_EXT_LOOPBACK,
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CAPS_HI_INT_LOOPBACK,
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CAPS_HI_EFUSE_AGENT,
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CAPS_HI_WOL_TIMER,
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CAPS_HI_STATISTICS,
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CAPS_HI_TRANSACTION_ID,
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};
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struct aq_hw_s;
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struct aq_fw_ops;
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struct aq_hw_caps_s;
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@ -222,7 +280,10 @@ int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
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int hw_atl_utils_update_stats(struct aq_hw_s *self);
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struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
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int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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u32 *p, u32 cnt);
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extern const struct aq_fw_ops aq_fw_1x_ops;
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extern const struct aq_fw_ops aq_fw_2x_ops;
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#endif /* HW_ATL_UTILS_H */
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@ -0,0 +1,184 @@
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
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* Atlantic hardware abstraction layer.
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*/
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#include "../aq_hw.h"
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#include "../aq_hw_utils.h"
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#include "../aq_pci_func.h"
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#include "../aq_ring.h"
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#include "../aq_vec.h"
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#include "hw_atl_utils.h"
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#include "hw_atl_llh.h"
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#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
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#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
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#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
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#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
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#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
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#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
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static int aq_fw2x_init(struct aq_hw_s *self)
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{
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int err = 0;
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/* check 10 times by 1ms */
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AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
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aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
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1000U, 10U);
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return err;
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}
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static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
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{
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enum hw_atl_fw2x_rate rate = 0;
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if (speed & AQ_NIC_RATE_10G)
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rate |= FW2X_RATE_10G;
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if (speed & AQ_NIC_RATE_5G)
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rate |= FW2X_RATE_5G;
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if (speed & AQ_NIC_RATE_5GSR)
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rate |= FW2X_RATE_5G;
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if (speed & AQ_NIC_RATE_2GS)
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rate |= FW2X_RATE_2G5;
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if (speed & AQ_NIC_RATE_1G)
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rate |= FW2X_RATE_1G;
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if (speed & AQ_NIC_RATE_100M)
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rate |= FW2X_RATE_100M;
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return rate;
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}
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static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
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{
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u32 val = link_speed_mask_2fw2x_ratemask(speed);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
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return 0;
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}
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state)
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{
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/* No explicit state in 2x fw */
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return 0;
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}
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static int aq_fw2x_update_link_status(struct aq_hw_s *self)
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{
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u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
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u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
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FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
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struct aq_hw_link_status_s *link_status = &self->aq_link_status;
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if (speed) {
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if (speed & FW2X_RATE_10G)
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link_status->mbps = 10000;
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else if (speed & FW2X_RATE_5G)
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link_status->mbps = 5000;
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else if (speed & FW2X_RATE_2G5)
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link_status->mbps = 2500;
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else if (speed & FW2X_RATE_1G)
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link_status->mbps = 1000;
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else if (speed & FW2X_RATE_100M)
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link_status->mbps = 100;
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else
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link_status->mbps = 10000;
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} else {
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link_status->mbps = 0;
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}
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return 0;
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}
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int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
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{
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int err = 0;
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u32 h = 0U;
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u32 l = 0U;
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u32 mac_addr[2] = { 0 };
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u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
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if (efuse_addr != 0) {
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err = hw_atl_utils_fw_downld_dwords(self,
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efuse_addr + (40U * 4U),
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mac_addr,
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ARRAY_SIZE(mac_addr));
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if (err)
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return err;
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mac_addr[0] = __swab32(mac_addr[0]);
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mac_addr[1] = __swab32(mac_addr[1]);
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}
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ether_addr_copy(mac, (u8 *)mac_addr);
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if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
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unsigned int rnd = 0;
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get_random_bytes(&rnd, sizeof(unsigned int));
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l = 0xE3000000U
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| (0xFFFFU & rnd)
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| (0x00 << 16);
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h = 0x8001300EU;
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mac[5] = (u8)(0xFFU & l);
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l >>= 8;
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mac[4] = (u8)(0xFFU & l);
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l >>= 8;
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mac[3] = (u8)(0xFFU & l);
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l >>= 8;
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mac[2] = (u8)(0xFFU & l);
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mac[1] = (u8)(0xFFU & h);
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h >>= 8;
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mac[0] = (u8)(0xFFU & h);
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}
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return err;
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}
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static int aq_fw2x_update_stats(struct aq_hw_s *self)
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{
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int err = 0;
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u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
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/* Toggle statistics bit for FW to update */
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mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
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aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
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/* Wait FW to report back */
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AQ_HW_WAIT_FOR(orig_stats_val !=
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(aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
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BIT(CAPS_HI_STATISTICS)),
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1U, 10000U);
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if (err)
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return err;
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return hw_atl_utils_update_stats(self);
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}
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const struct aq_fw_ops aq_fw_2x_ops = {
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.init = aq_fw2x_init,
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.reset = NULL,
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.get_mac_permanent = aq_fw2x_get_mac_permanent,
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.set_link_speed = aq_fw2x_set_link_speed,
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.set_state = aq_fw2x_set_state,
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.update_link_status = aq_fw2x_update_link_status,
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.update_stats = aq_fw2x_update_stats,
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};
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