ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus <noamc@ezchip.com>
This commit is contained in:
Noam Camus
Vineet Gupta
parent
8bcf2c48f3
commit
a5a10d99a9
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@ -17,6 +17,8 @@
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#define atomic_read(v) READ_ONCE((v)->counter)
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#ifdef CONFIG_ARC_HAS_LLSC
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@ -180,13 +182,88 @@ ATOMIC_OP(andnot, &= ~, bic)
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ATOMIC_OP(or, |=, or)
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ATOMIC_OP(xor, ^=, xor)
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#undef SCOND_FAIL_RETRY_VAR_DEF
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#undef SCOND_FAIL_RETRY_ASM
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#undef SCOND_FAIL_RETRY_VARS
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline int atomic_read(const atomic_t *v)
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{
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int temp;
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__asm__ __volatile__(
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" ld.di %0, [%1]"
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: "=r"(temp)
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: "r"(&v->counter)
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: "memory");
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return temp;
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}
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static inline void atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__(
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" st.di %0,[%1]"
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:
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: "r"(i), "r"(&v->counter)
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: "memory");
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}
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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: \
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: "r"(i), "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned int temp = i; \
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\
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/* Explicit full memory barrier needed before/after */ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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" mov %0, r2" \
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: "+r"(temp) \
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: "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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\
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smp_mb(); \
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\
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temp c_op i; \
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\
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return temp; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
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#define atomic_sub(i, v) atomic_add(-(i), (v))
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#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
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ATOMIC_OP(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
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#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
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ATOMIC_OP(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
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ATOMIC_OP(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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@ -22,7 +22,7 @@
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#include <asm/smp.h>
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#endif
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#if defined(CONFIG_ARC_HAS_LLSC)
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#ifdef CONFIG_ARC_HAS_LLSC
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/*
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* Hardware assisted Atomic-R-M-W
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@ -88,7 +88,7 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *
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return (old & (1 << nr)) != 0; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#elif !defined(CONFIG_ARC_PLAT_EZNPS)
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/*
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* Non hardware assisted Atomic-R-M-W
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@ -139,7 +139,55 @@ static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *
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return (old & (1UL << (nr & 0x1f))) != 0; \
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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#else /* CONFIG_ARC_PLAT_EZNPS */
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#define BIT_OP(op, c_op, asm_op) \
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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m += nr >> 5; \
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\
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nr = (1UL << (nr & 0x1f)); \
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if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \
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nr = ~nr; \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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: \
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: "r"(nr), "r"(m), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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}
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#define TEST_N_BIT_OP(op, c_op, asm_op) \
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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{ \
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unsigned long old; \
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\
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m += nr >> 5; \
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\
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nr = old = (1UL << (nr & 0x1f)); \
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if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \
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old = ~old; \
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\
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/* Explicit full memory barrier needed before/after */ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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" mov %0, r2" \
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: "+r"(old) \
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: "r"(m), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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\
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smp_mb(); \
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\
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return (old & nr) != 0; \
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}
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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/***************************************
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* Non atomic variants
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@ -181,9 +229,15 @@ static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long
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/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
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__TEST_N_BIT_OP(op, c_op, asm_op)
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#ifndef CONFIG_ARC_PLAT_EZNPS
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BIT_OPS(set, |, bset)
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BIT_OPS(clear, & ~, bclr)
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BIT_OPS(change, ^, bxor)
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#else
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BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3)
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BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3)
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BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3)
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#endif
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/*
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* This routine doesn't need to be atomic.
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@ -44,7 +44,7 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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return prev;
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}
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#else
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#elif !defined(CONFIG_ARC_PLAT_EZNPS)
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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@ -64,23 +64,48 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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return prev;
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}
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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/*
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* Explicit full memory barrier needed before/after
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*/
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smp_mb();
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write_aux_reg(CTOP_AUX_GPA1, expected);
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__asm__ __volatile__(
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" mov r2, %0\n"
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" mov r3, %1\n"
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" .word %2\n"
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" mov %0, r2"
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: "+r"(new)
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: "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3)
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: "r2", "r3", "memory");
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smp_mb();
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return new;
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
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(unsigned long)(o), (unsigned long)(n)))
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/*
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* Since not supported natively, ARC cmpxchg() uses atomic_ops_lock (UP/SMP)
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* just to gaurantee semantics.
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* atomic_cmpxchg() needs to use the same locks as it's other atomic siblings
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* which also happens to be atomic_ops_lock.
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*
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* Thus despite semantically being different, implementation of atomic_cmpxchg()
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* is same as cmpxchg().
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* atomic_cmpxchg is same as cmpxchg
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* LLSC: only different in data-type, semantics are exactly same
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* !LLSC: cmpxchg() has to use an external lock atomic_ops_lock to guarantee
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* semantics, and this lock also happens to be used by atomic_*()
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*/
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#ifndef CONFIG_ARC_PLAT_EZNPS
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/*
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* xchg (reg with memory) based on "Native atomic" EX insn
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*/
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@ -143,6 +168,41 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
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#endif
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
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int size)
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{
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extern unsigned long __xchg_bad_pointer(void);
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switch (size) {
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case 4:
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/*
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* Explicit full memory barrier needed before/after
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*/
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smp_mb();
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__asm__ __volatile__(
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" mov r2, %0\n"
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" mov r3, %1\n"
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" .word %2\n"
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" mov %0, r2\n"
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: "+r"(val)
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: "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3)
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: "r2", "r3", "memory");
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smp_mb();
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return val;
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}
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return __xchg_bad_pointer();
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}
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#define xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
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sizeof(*(ptr))))
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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/*
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* "atomic" variant of xchg()
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* REQ: It needs to follow the same serialization rules as other atomic_xxx()
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