clk: samsung: exynos4: export sclk_hdmiphy clock
Export sclk_hdmiphy clock to be usable from DT. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
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/* fixed rate clocks generated inside the soc */
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static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
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FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
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FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
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FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
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FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
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};
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@ -33,6 +33,7 @@
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#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
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#define CLK_MOUT_CORE 19
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#define CLK_MOUT_APLL 20
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#define CLK_SCLK_HDMIPHY 22
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_FIMC0 128
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