Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that do not match the hardware's capabilities, as well as some general rk3399 pcie fixes as well as also the mmc resets. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY6c0QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgdIYB/wKt/kONmWhi3RsXCXFUv/PBM0NToKvUq5e 5LvprMvIb/dyEBpA1bSaxOmktYDmEzqQFfxBOT7gfWX8/N+oFLWsfLsMNGkReev0 QPxQaITA1sOVSqDPWb5Pw4jDJ58CKUH1Cvj9GU1NuU3qp5ioggMTr/RFk2FsQ2wi AJTDmyRHIp2Hfr7C//H85U7qd0NB0xQJz4GpZ98HnuZoSzpeQs7SRikOr4PZAaEA mqsFizsELiAee/BmsTsppjzEIM5MpCIe91fx4S5NBNbnbmy2pFvXsmL5QazTWyao FiWPPcIWuEVnuVLWXAGn4vLlKJG7DH+aJSOtN482J/fRnaTZABU6 =/nLm -----END PGP SIGNATURE----- Merge tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Pull "Rockchip dts64 updates for 4.12 part1" from Heiko Stübner: Contains various changes for the rk3368 (dma, i2s, disable mailbox per default, mmc-resets) and also removes the wrongly added idle states, that do not match the hardware's capabilities, as well as some general rk3399 pcie fixes as well as also the mmc resets. * tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix PCIe domain number for rk3399 arm64: dts: rockchip: add rk3399 dw-mmc resets arm64: dts: rockchip: add rk3368 dw-mmc resets arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs arm64: dts: rockchip: add dmac nodes for rk3368 SoCs arm64: dts: rockchip: remove wrongly added idle states on rk3368 arm64: dts: rockchip: sort rk3399-pcie by unit address
This commit is contained in:
Arnd Bergmann
commit
a5cd01ff18
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@ -108,23 +108,10 @@ core3 {
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};
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <0x3fffffff>;
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exit-latency-us = <0x40000000>;
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min-residency-us = <0xffffffff>;
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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@ -134,7 +121,6 @@ cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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@ -142,7 +128,6 @@ cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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@ -150,7 +135,6 @@ cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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@ -158,7 +142,6 @@ cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x100>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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@ -168,7 +151,6 @@ cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x101>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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@ -176,7 +158,6 @@ cpu_b2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x102>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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@ -184,11 +165,39 @@ cpu_b3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x103>;
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cpu-idle-states = <&cpu_sleep>;
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enable-method = "psci";
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff250000 0x0 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC_PERI>;
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clock-names = "apb_pclk";
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};
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dmac_bus: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff600000 0x0 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC_BUS>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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@ -237,6 +246,8 @@ sdmmc: dwmmc@ff0c0000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_MMC0>;
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reset-names = "reset";
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status = "disabled";
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};
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@ -249,6 +260,8 @@ sdio0: dwmmc@ff0d0000 {
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_SDIO0>;
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reset-names = "reset";
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status = "disabled";
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};
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@ -261,6 +274,8 @@ emmc: dwmmc@ff0f0000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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@ -631,6 +646,7 @@ mbox: mbox@ff6b0000 {
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clocks = <&cru PCLK_MAILBOX>;
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clock-names = "pclk_mailbox";
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#mbox-cells = <1>;
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status = "disabled";
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};
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pmugrf: syscon@ff738000 {
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@ -684,6 +700,30 @@ timer@ff810000 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2s_2ch: i2s-2ch@ff890000 {
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compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
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reg = <0x0 0xff890000 0x0 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
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dmas = <&dmac_bus 6>, <&dmac_bus 7>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2s_8ch: i2s-8ch@ff898000 {
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compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
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reg = <0x0 0xff898000 0x0 0x1000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
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dmas = <&dmac_bus 0>, <&dmac_bus 1>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s_8ch_bus>;
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status = "disabled";
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};
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gic: interrupt-controller@ffb71000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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@ -886,6 +926,20 @@ i2c5_xfer: i2c5-xfer {
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};
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};
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i2s {
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i2s_8ch_bus: i2s-8ch-bus {
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rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
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<2 13 RK_FUNC_1 &pcfg_pull_none>,
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<2 14 RK_FUNC_1 &pcfg_pull_none>,
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<2 15 RK_FUNC_1 &pcfg_pull_none>,
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<2 16 RK_FUNC_1 &pcfg_pull_none>,
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<2 17 RK_FUNC_1 &pcfg_pull_none>,
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<2 18 RK_FUNC_1 &pcfg_pull_none>,
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<2 19 RK_FUNC_1 &pcfg_pull_none>,
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<2 20 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
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@ -211,6 +211,51 @@ dmac_peri: dma-controller@ff6e0000 {
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};
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};
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pcie0: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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reg = <0x0 0xf8000000 0x0 0x2000000>,
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<0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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aspm-no-l0s;
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bus-range = <0x0 0x1>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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linux,pci-domain = <0>;
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max-link-speed = <1>;
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msi-map = <0x0 &its 0x0 0x1000>;
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
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<&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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status = "disabled";
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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gmac: ethernet@fe300000 {
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compatible = "rockchip,rk3399-gmac";
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reg = <0x0 0xfe300000 0x0 0x10000>;
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@ -241,6 +286,8 @@ sdio0: dwmmc@fe310000 {
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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resets = <&cru SRST_SDIO0>;
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reset-names = "reset";
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status = "disabled";
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};
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@ -255,6 +302,8 @@ sdmmc: dwmmc@fe320000 {
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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power-domains = <&power RK3399_PD_SD>;
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resets = <&cru SRST_SDMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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@ -275,50 +324,6 @@ sdhci: sdhci@fe330000 {
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status = "disabled";
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};
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pcie0: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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reg = <0x0 0xf8000000 0x0 0x2000000>,
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<0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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aspm-no-l0s;
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bus-range = <0x0 0x1>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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max-link-speed = <1>;
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msi-map = <0x0 &its 0x0 0x1000>;
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
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<&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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status = "disabled";
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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usb_host0_ehci: usb@fe380000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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Loading…
Reference in New Issue