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irqchip fixes for 5.3 

- Fix a couple of UAF on error paths (RZA1, GICv3 ITS)
 - Fix iMX GPCv2 trigger setting
 - Add missing of_node_put on error path in MBIGEN
 - Add another bunch of /* fall-through */ to silence warnings
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Merge tag 'irqchip-fixes-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

  A small bunch of fixes from the irqchip department:

    - Fix a couple of UAF on error paths (RZA1, GICv3 ITS)
    - Fix iMX GPCv2 trigger setting
    - Add missing of_node_put on error path in MBIGEN
    - Add another bunch of /* fall-through */ to silence warnings
This commit is contained in:
Thomas Gleixner 2019-08-01 20:21:00 +02:00
parent 5f9e832c13 b5fa9fc9e8
commit a5dbba8f44
4 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/irqchip/irq-gic-v3-its.c
View File

@ -3010,7 +3010,7 @@ static int its_vpe_init(struct its_vpe *vpe)
if (!its_alloc_vpe_table(vpe_id)) { if (!its_alloc_vpe_table(vpe_id)) {
its_vpe_id_free(vpe_id); its_vpe_id_free(vpe_id);
its_free_pending_table(vpe->vpt_page); its_free_pending_table(vpt_page);
return -ENOMEM; return -ENOMEM;
} }

4
drivers/irqchip/irq-gic-v3.c
View File

@ -771,8 +771,10 @@ static void gic_cpu_sys_reg_init(void)
case 7: case 7:
write_gicreg(0, ICC_AP0R3_EL1); write_gicreg(0, ICC_AP0R3_EL1);
write_gicreg(0, ICC_AP0R2_EL1); write_gicreg(0, ICC_AP0R2_EL1);
/* Fall through */
case 6: case 6:
write_gicreg(0, ICC_AP0R1_EL1); write_gicreg(0, ICC_AP0R1_EL1);
/* Fall through */
case 5: case 5:
case 4: case 4:
write_gicreg(0, ICC_AP0R0_EL1); write_gicreg(0, ICC_AP0R0_EL1);
@ -786,8 +788,10 @@ static void gic_cpu_sys_reg_init(void)
case 7: case 7:
write_gicreg(0, ICC_AP1R3_EL1); write_gicreg(0, ICC_AP1R3_EL1);
write_gicreg(0, ICC_AP1R2_EL1); write_gicreg(0, ICC_AP1R2_EL1);
/* Fall through */
case 6: case 6:
write_gicreg(0, ICC_AP1R1_EL1); write_gicreg(0, ICC_AP1R1_EL1);
/* Fall through */
case 5: case 5:
case 4: case 4:
write_gicreg(0, ICC_AP1R0_EL1); write_gicreg(0, ICC_AP1R0_EL1);

1
drivers/irqchip/irq-imx-gpcv2.c
View File

@ -131,6 +131,7 @@ static struct irq_chip gpcv2_irqchip_data_chip = {
.irq_unmask = imx_gpcv2_irq_unmask, .irq_unmask = imx_gpcv2_irq_unmask,
.irq_set_wake = imx_gpcv2_irq_set_wake, .irq_set_wake = imx_gpcv2_irq_set_wake,
.irq_retrigger = irq_chip_retrigger_hierarchy, .irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = irq_chip_set_type_parent,
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
.irq_set_affinity = irq_chip_set_affinity_parent, .irq_set_affinity = irq_chip_set_affinity_parent,
#endif #endif

9
drivers/irqchip/irq-mbigen.c
View File

@ -241,12 +241,15 @@ static int mbigen_of_create_domain(struct platform_device *pdev,
parent = platform_bus_type.dev_root; parent = platform_bus_type.dev_root;
child = of_platform_device_create(np, NULL, parent); child = of_platform_device_create(np, NULL, parent);
if (!child) if (!child) {
of_node_put(np);
return -ENOMEM; return -ENOMEM;
}
if (of_property_read_u32(child->dev.of_node, "num-pins", if (of_property_read_u32(child->dev.of_node, "num-pins",
&num_pins) < 0) { &num_pins) < 0) {
dev_err(&pdev->dev, "No num-pins property\n"); dev_err(&pdev->dev, "No num-pins property\n");
of_node_put(np);
return -EINVAL; return -EINVAL;
} }
@ -254,8 +257,10 @@ static int mbigen_of_create_domain(struct platform_device *pdev,
mbigen_write_msg, mbigen_write_msg,
&mbigen_domain_ops, &mbigen_domain_ops,
mgn_chip); mgn_chip);
if (!domain) if (!domain) {
of_node_put(np);
return -ENOMEM; return -ENOMEM;
}
} }
return 0; return 0;