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drm/msm/mdp5: only flush on a CRTC ->atomic_flush() 

MDP5 hardware has some limitation and requires to avoid flushing
registers more than once between two Vblanks.

This change removes all FLUSH operations (except for HW cursor)
beside the one coming from a CRTC's ->atomic_flush().

This avoid this type of behavior (eg: CRTC + 1 plane overlay):

	[drm:mdp5_crtc_vblank_irq] vblank
	[drm:mdp5_ctl_commit] flush (20048)   CTL + LM0 + RGB0
	[drm:mdp5_ctl_commit] flush (20040)   CTL + LM0
	[drm:mdp5_crtc_vblank_irq] blank
	[drm:mdp5_ctl_commit] flush (20049)   CTL + LM0 + RGB0 + VIG0
	[drm:mdp5_crtc_vblank_irq] blank

and replaces it by:

	[drm:mdp5_crtc_vblank_irq] vblank
	[drm:mdp5_ctl_commit] flush (20048)   CTL + LM0 + RGB0
	[drm:mdp5_crtc_vblank_irq] blank
	[drm:mdp5_ctl_commit] flush (20049)   CTL + LM0 + RGB0 + VIG0
	[drm:mdp5_crtc_vblank_irq] blank

Only *one* FLUSH is called between Vblanks interrupts.

Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Stephane Viau 2015-01-27 11:35:56 -05:00 committed by Rob Clark
parent 034c5150ae
commit a73f3382da
1 changed files with 0 additions and 7 deletions
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7
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
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@ -298,8 +298,6 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc)
mdp5_enable(mdp5_kms);
mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
crtc_flush_all(crtc);
mdp5_crtc->enabled = true;
}
@ -618,7 +616,6 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
{
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
uint32_t flush_mask = 0;
uint32_t intf_sel;
unsigned long flags;
@ -657,10 +654,6 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
crtc_flush(crtc, flush_mask);
}
int mdp5_crtc_get_lm(struct drm_crtc *crtc)