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dt-bindings: phy: Clarify ULPI PHY source clock 

cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group.
PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the
DAP_MCLK2 pad.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Marcel Ziswiler 2018-02-22 15:38:25 +01:00 committed by Thierry Reding
parent ff0286cbcc
commit a7ca2a709d
1 changed files with 3 additions and 1 deletions
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4
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
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@ -21,7 +21,9 @@ Required properties :
- timer: The timeout clock (clk_m). Present if phy_type == utmi. - timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers. - utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi. Present if phy_type == utmi.
- ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
"nvidia,function" pllp_out4).
Present if phy_type == ulpi, and ULPI link mode is in use. Present if phy_type == ulpi, and ULPI link mode is in use.
- resets : Must contain an entry for each entry in reset-names. - resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details. See ../reset/reset.txt for details.