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media: i2c: adv748x: Conditionally enable only CSI-2 outputs 

The ADV748x has two CSI-2 output port and one TTL input/output port for
digital video reception/transmission. The TTL digital pad is unconditionally
enabled during the device reset even if not used. Same goes for the TXA
and TXB CSI-2 outputs, which are enabled by the initial settings blob
programmed into the chip.

In order to improve power saving, do not enable unused output interfaces:
keep TTL output disabled, as it is not used, and drop CSI-2 output enabling
from the initial settings list, as they get conditionally enabled later.

Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Jacopo Mondi 2018-09-17 07:30:56 -04:00 committed by Mauro Carvalho Chehab
parent 6bc3ea7a61
commit a7f9d21e9e
1 changed files with 1 additions and 7 deletions
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8
drivers/media/i2c/adv748x/adv748x-core.c
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@ -382,8 +382,6 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = {
{ADV748X_PAGE_IO, 0x0c, 0xe0}, /* Enable LLC_DLL & Double LLC Timing */ {ADV748X_PAGE_IO, 0x0c, 0xe0}, /* Enable LLC_DLL & Double LLC Timing */
{ADV748X_PAGE_IO, 0x0e, 0xdd}, /* LLC/PIX/SPI PINS TRISTATED AUD */ {ADV748X_PAGE_IO, 0x0e, 0xdd}, /* LLC/PIX/SPI PINS TRISTATED AUD */
/* Outputs Enabled */
{ADV748X_PAGE_IO, 0x10, 0xa0}, /* Enable 4-lane CSI Tx & Pixel Port */
{ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */
{ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */
@ -437,10 +435,6 @@ static const struct adv748x_reg_value adv748x_init_txb_1lane[] = {
{ADV748X_PAGE_SDP, 0x31, 0x12}, /* ADI Required Write */ {ADV748X_PAGE_SDP, 0x31, 0x12}, /* ADI Required Write */
{ADV748X_PAGE_SDP, 0xe6, 0x4f}, /* V bit end pos manually in NTSC */ {ADV748X_PAGE_SDP, 0xe6, 0x4f}, /* V bit end pos manually in NTSC */
/* Enable 1-Lane MIPI Tx, */
/* enable pixel output and route SD through Pixel port */
{ADV748X_PAGE_IO, 0x10, 0x70},
{ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */ {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */
{ADV748X_PAGE_TXB, 0x00, 0xa1}, /* Set Auto DPHY Timing */ {ADV748X_PAGE_TXB, 0x00, 0xa1}, /* Set Auto DPHY Timing */
{ADV748X_PAGE_TXB, 0xd2, 0x40}, /* ADI Required Write */ {ADV748X_PAGE_TXB, 0xd2, 0x40}, /* ADI Required Write */
@ -465,7 +459,7 @@ static const struct adv748x_reg_value adv748x_init_txb_1lane[] = {
static int adv748x_reset(struct adv748x_state *state) static int adv748x_reset(struct adv748x_state *state)
{ {
int ret; int ret;
u8 regval = ADV748X_IO_10_PIX_OUT_EN; u8 regval = 0;
ret = adv748x_write_regs(state, adv748x_sw_reset); ret = adv748x_write_regs(state, adv748x_sw_reset);
if (ret < 0) if (ret < 0)