MIPS: CPS: Warn if a core doesn't start
When debugging core bringup it is useful to see the state of the CPC sequencer, so output that value if the core hasn't started within a reasonable amount of time (1 second). This avoids simply appearing to the user to hang if a secondary core fails to start. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -8,6 +8,7 @@
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/sched.h>
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@ -188,7 +189,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
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static void boot_core(unsigned core)
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{
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u32 access;
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u32 access, stat, seq_state;
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unsigned timeout;
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/* Select the appropriate core */
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write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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@ -208,6 +210,28 @@ static void boot_core(unsigned core)
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/* Reset the core */
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mips_cpc_lock_other(core);
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write_cpc_co_cmd(CPC_Cx_CMD_RESET);
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timeout = 100;
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while (true) {
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stat = read_cpc_co_stat_conf();
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seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
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/* U6 == coherent execution, ie. the core is up */
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if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
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break;
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/* Delay a little while before we start warning */
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if (timeout) {
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timeout--;
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mdelay(10);
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continue;
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}
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pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
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core, stat);
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mdelay(1000);
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}
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mips_cpc_unlock_other();
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} else {
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/* Take the core out of reset */
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