drm/nv50: restore correct cache1 get/put address on fifoctx load
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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parent
c03ec7f91f
commit
a908b96c22
drivers/gpu/drm/nouveau
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@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
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nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
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nv_ro32(dev, cache, (ptr * 2) + 1));
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}
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nv_wr32(dev, 0x3210, cnt << 2);
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nv_wr32(dev, 0x3270, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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/* guessing that all the 0x34xx regs aren't on NV50 */
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if (!IS_G80) {
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@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
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dev_priv->engine.instmem.finish_access(dev);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
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return 0;
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}
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