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ARM: 64-bit DT updates 

Device-tree updates for arm64 platforms. For the first time I can
 remember, this is actually larger than the corresponding branch for
 32-bit platforms overall, though that has more individual changes.
 
 A significant portion this time is due to added machine support:
 
 - Initial support for the Realtek RTD1295 SoC, along with the Zidoo
   X9S set-top-box
 
 - Initial support for Actions Semi S900 and the Bubblegum-96
   single-board-cёmputer.
 
 - Rockchips support for the rk3399-Firefly single-board-computer
   gets added, this one stands out for being relatively fast,
   affordable and well₋supported, compared to many boards that
   only fall into one or two of the above categories.
 
 - Mediatek gains support for the mt6797 mobile-phone SoC platform
   and corresponding evaluation board.
 
 - Amlogic board support gets added for the NanoPi K2 and S905x
   LibreTech CC single-board computers and the R-Box Pro set-top-box
 
 - Allwinner board support gets added for the OrangePi Win,
   Orangepi Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single
   board computers and the SoPine system-on-module.
 
 - Renesas board support for Salvator-XS and H3ULCB
   automotive development systems.
 
 - Socionext Uniphier board support for LD11-global and LD20-global,
   whatever those may be.
 
 - Broadcom adds support for the new Stingray communication processor
   in its iProc family, along with two reference boards.
 
 Other updates include:
 
 - For the hisicon platform, support for Hi3660-Hikey960 gets
   extended significantly.
 
 - Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
   Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAWVpZnmCrR//JCVInAQJYsBAAhuoRK5WZawkeAMEbkGeyOXYbnp6qUlKm
 w1lwXXdStLjkOUmQXo5KNDmWiHbPnuhwHprX9HMPDI0G1+DSaOlxIezNFIlKOUyW
 fQxZjt4+L3eRXQCetj3P+QAp37ifmFxSg0RmM+fGBwAhNcyf6nH98cn4ZaauZrfu
 F3cJz9t9MTdIlxXXF1uTAk9g9tR8sCoD4ekmM15MwtLZZTqmZNP1OelRDwwzNoOn
 6pp4BUDOFhesynsI7uYoKdj0lt0fGg348FAlt9w1g9xQ819wrdaz/eAmV49eUZQ+
 Ps8FY1OvJsVaoe3yGeEG0Ps87VTRCzSOFqstNDftYsz+q5Mm8ImEwG8JhuoqyDQD
 /VW+DamdXyN4tuUFQfg+Cz8+6WZRwfTeOVmuvC4aRuKNDWV5CC5qP1B7oZ/a2nYR
 6M8+1W+RJOgjJ9wa/125Z6edEpzCRzfxDSLKyHbQ2q//0NK0kRrS9+Rdi6FlReV3
 mVGtK5gFLVzcCyBSaMY48KnRe0/cjOZ5YXw5o/DIeYJkyPnOlN1pXOEMalQCf+uI
 6D8pjO307lt6TLCiq3i2C8bN5k0FBqD4rirsp9PlRw3vTx1LI+KnhJQ8NOrrTheW
 gtDevoDMssnJdmVj3Wbv8DPWJOGSF6vA/xvsQBe0MglHFtuR/0jp9YC8ncvIP1RC
 CkFTqmpZXYg=
 =E8pa
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "Device-tree updates for arm64 platforms. For the first time I can
  remember, this is actually larger than the corresponding branch for
  32-bit platforms overall, though that has more individual changes.

  A significant portion this time is due to added machine support:

   - Initial support for the Realtek RTD1295 SoC, along with the Zidoo
     X9S set-top-box

   - Initial support for Actions Semi S900 and the Bubblegum-96
     single-board-cёmputer.

   - Rockchips support for the rk3399-Firefly single-board-computer gets
     added, this one stands out for being relatively fast, affordable
     and well₋supported, compared to many boards that only fall into one
     or two of the above categories.

   - Mediatek gains support for the mt6797 mobile-phone SoC platform and
     corresponding evaluation board.

   - Amlogic board support gets added for the NanoPi K2 and S905x
     LibreTech CC single-board computers and the R-Box Pro set-top-box

   - Allwinner board support gets added for the OrangePi Win, Orangepi
     Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers
     and the SoPine system-on-module.

   - Renesas board support for Salvator-XS and H3ULCB automotive
     development systems.

   - Socionext Uniphier board support for LD11-global and LD20-global,
     whatever those may be.

   - Broadcom adds support for the new Stingray communication processor
     in its iProc family, along with two reference boards.

  Other updates include:

   - For the hisicon platform, support for Hi3660-Hikey960 gets extended
     significantly.

   - Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier,
     Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits)
  ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
  Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"
  arm64: dts: mediatek: don't include missing file
  ARM64: dts: meson-gxl: Add Libre Technology CC support
  dt-bindings: arm: amlogic: Add Libre Technology CC board
  dt-bindings: add Libre Technology vendor prefix
  arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
  arm64: dts: zte: Use - instead of @ for DT OPP entries
  arm64: dts: marvell: add gpio support for Armada 7K/8K
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  arm64: dts: marvell: use new binding for the system controller on cp110
  arm64: dts: marvell: remove *-clock-output-names on cp110
  arm64: dts: marvell: use new bindings for xor clocks on ap806
  arm64: dts: marvell: mcbin: enable the mdio node
  arm64: dts: Add Actions Semi S900 and Bubblegum-96
  dt-bindings: Add vendor prefix for uCRobotics
  arm64: dts: marvell: add xmdio nodes for 7k/8k
  arm64: dts: marvell: add a comment on the cp110 slave node status
  arm64: dts: marvell: remove cpm crypto nodes from dts files
  arm64: dts: marvell: cp110: enable the crypto engine at the SoC level
  ...
This commit is contained in:
Linus Torvalds 2017-07-04 14:50:59 -07:00
parent e854711291 ac548add22
commit a9ceea2674
171 changed files with 11444 additions and 2380 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Documentation/devicetree/bindings/arm/amlogic.txt
View File

@ -29,26 +29,35 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
Board compatible values:
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
- "tronfy,mxq" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
- "friendlyarm,nanopi-k2" (Meson gxbb)
- "hardkernel,odroid-c2" (Meson gxbb)
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
- "wetek,hub" (Meson gxbb)
- "wetek,play2" (Meson gxbb)
- "amlogic,p212" (Meson gxl s905x)
- "hwacom,amazetv" (Meson gxl s905x)
- "khadas,vim" (Meson gxl s905x)
- "libretech,cc" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "hwacom,amazetv" (Meson gxl s905x)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)

12
Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt Normal file
View File

@ -0,0 +1,12 @@
Broadcom Stingray device tree bindings
------------------------------------------------
Boards with Stingray shall have the following properties:
Required root node property:
Stingray Combo SVK board
compatible = "brcm,bcm958742k", "brcm,stingray";
Stingray SST100 board
compatible = "brcm,bcm958742t", "brcm,stingray";

4
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -4,6 +4,10 @@ Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";

8
Documentation/devicetree/bindings/arm/mediatek.txt
View File

@ -12,6 +12,8 @@ compatible: Must contain one of
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
"mediatek,mt7623"
"mediatek,mt8127"
"mediatek,mt8135"
@ -38,6 +40,12 @@ Supported boards:
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Evaluation board for MT7623:
Required root node properties:
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";

20
Documentation/devicetree/bindings/arm/realtek.txt Normal file
View File

@ -0,0 +1,20 @@
Realtek platforms device tree bindings
--------------------------------------
RTD1295 SoC
===========
Required root node properties:
- compatible : must contain "realtek,rtd1295"
Root node property compatible must contain, depending on board:
- Zidoo X9S: "zidoo,x9s"
Example:
compatible = "zidoo,x9s", "realtek,rtd1295";

4
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -42,6 +42,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
- Firefly Firefly-RK3399 board:
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";

2
Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
View File

@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.

76
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
View File

@ -219,3 +219,79 @@ BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
Stingray
-----------
PLL and leaf clock compatible strings for Stingray are:
"brcm,sr-genpll0"
"brcm,sr-genpll1"
"brcm,sr-genpll2"
"brcm,sr-genpll3"
"brcm,sr-genpll4"
"brcm,sr-genpll5"
"brcm,sr-genpll6"
"brcm,sr-lcpll0"
"brcm,sr-lcpll1"
"brcm,sr-lcpll-pcie"
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK

10
Documentation/devicetree/bindings/i2c/i2c-mt6577.txt → Documentation/devicetree/bindings/i2c/i2c-mtk.txt
View File

@ -4,11 +4,11 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
(a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
(b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
(c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
(d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
(e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
"mediatek,mt6577-i2c": for i2c compatible with mt6577.
"mediatek,mt6589-i2c": for i2c compatible with mt6589.
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
"mediatek,mt8173-i2c": for i2c compatible with mt8173.
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.

28
Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
View File

@ -1,21 +1,23 @@
+Mediatek 65xx/67xx/81xx sysirq
+Mediatek MT65xx/MT67xx/MT81xx sysirq
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
- compatible: should be one of:
"mediatek,mt8173-sysirq"
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
"mediatek,mt6795-sysirq"
"mediatek,mt6755-sysirq"
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
- compatible: should be
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- interrupt-parent: phandle of irq parent for sysirq. The parent must

4
Documentation/devicetree/bindings/mfd/hi6421.txt
View File

@ -1,7 +1,9 @@
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
Required parent device properties:
- compatible : contains "hisilicon,hi6421-pmic";
- compatible : One of the following chip-specific strings:
"hisilicon,hi6421-pmic";
"hisilicon,hi6421v530-pmic";
- reg : register range space of hi6421;
Supported Hi6421 sub-devices include:

14
Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
View File

@ -7,6 +7,20 @@ This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc driver.
Required properties:
- compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
Possible compatibles for PowerPC:
"fsl,mpc8536-esdhc"
"fsl,mpc8378-esdhc"
"fsl,p2020-esdhc"
"fsl,p4080-esdhc"
"fsl,t1040-esdhc"
"fsl,t4240-esdhc"
Possible compatibles for ARM:
"fsl,ls1012a-esdhc"
"fsl,ls1088a-esdhc"
"fsl,ls1043a-esdhc"
"fsl,ls1046a-esdhc"
"fsl,ls2080a-esdhc"
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.

1
Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
View File

@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be one of the following.
- "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.

50
Documentation/devicetree/bindings/pci/kirin-pcie.txt Normal file
View File

@ -0,0 +1,50 @@
HiSilicon Kirin SoCs PCIe host DT description
Kirin PCIe host controller is based on Designware PCI core.
It shares common functions with PCIe Designware core driver
and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
Additional properties are described here:
Required properties
- compatible:
"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
- reg: Should contain rc_dbi, apb, phy, config registers location and length.
- reg-names: Must include the following entries:
"dbi": controller configuration registers;
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
Optional properties:
Example based on kirin960:
pcie@f4000000 {
compatible = "hisilicon,kirin-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
reg-names = "dbi","apb","phy", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
<0x0 0 0 2 &gic 0 0 0 283 4>,
<0x0 0 0 3 &gic 0 0 0 284 4>,
<0x0 0 0 4 &gic 0 0 0 285 4>;
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
clock-names = "pcie_phy_ref", "pcie_aux",
"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
reset-gpios = <&gpio11 1 0 >;
};

2
Documentation/devicetree/bindings/serial/mtk-uart.txt
View File

@ -8,6 +8,8 @@ Required properties:
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6755-uart" for MT6755 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS

6
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -9,11 +9,14 @@ domain control.
The driver implements the Generic PM domain bindings described in
power/power_domain.txt. It provides the power domains defined in
include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt2701-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@ -22,6 +25,7 @@ Required properties:
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701: "mm", "mfg", "ethif"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:

4
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -166,6 +166,7 @@ keithkoep Keith & Koep GmbH
keymile Keymile GmbH
khadas Khadas
kinetic Kinetic Technologies
kingnovel Kingnovel Technology Co., Ltd.
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
@ -173,6 +174,7 @@ lantiq Lantiq Semiconductor
lego LEGO Systems A/S
lenovo Lenovo Group Ltd.
lg LG Corporation
libretech Shenzhen Libre Technology Co., Ltd
licheepi Lichee Pi
linaro Linaro Limited
linux Linux-specific binding
@ -332,6 +334,7 @@ tronfy Tronfy
tronsmart Tronsmart
truly Truly Semiconductors Limited
tyan Tyan Computer Corporation
ucrobotics uCRobotics
udoo Udoo
uniwest United Western Technologies Corp (UniWest)
upisemi uPI Semiconductor Corp.
@ -357,6 +360,7 @@ xlnx Xilinx
xunlong Shenzhen Xunlong Software CO.,Limited
zarlink Zarlink Semiconductor
zeitec ZEITEC Semiconductor Co., LTD.
zidoo Shenzhen Zidoo Technology Co., Ltd.
zii Zodiac Inflight Innovations
zte ZTE Corp.
zyxel ZyXEL Communications Corp.

2
arch/arm64/boot/dts/Makefile
View File

@ -1,3 +1,4 @@
dts-dirs += actions
dts-dirs += al
dts-dirs += allwinner
dts-dirs += altera
@ -14,6 +15,7 @@ dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += nvidia
dts-dirs += qcom
dts-dirs += realtek
dts-dirs += renesas
dts-dirs += rockchip
dts-dirs += socionext

5
arch/arm64/boot/dts/actions/Makefile Normal file
View File

@ -0,0 +1,5 @@
dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

35
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts Normal file
View File

@ -0,0 +1,35 @@
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "s900.dtsi"
/ {
compatible = "ucrobotics,bubblegum-96", "actions,s900";
model = "Bubblegum-96";
aliases {
serial5 = &uart5;
};
chosen {
stdout-path = "serial5:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&timer {
clocks = <&hosc>;
};
&uart5 {
status = "okay";
};

164
arch/arm64/boot/dts/actions/s900.dtsi Normal file
View File

@ -0,0 +1,164 @@
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "actions,s900";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secmon@1f000000 {
reg = <0x0 0x1f000000 0x0 0x1000000>;
no-map;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
hosc: hosc {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@e00f1000 {
compatible = "arm,gic-400";
reg = <0x0 0xe00f1000 0x0 0x1000>,
<0x0 0xe00f2000 0x0 0x2000>,
<0x0 0xe00f4000 0x0 0x2000>,
<0x0 0xe00f6000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
uart0: serial@e0120000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0120000 0x0 0x2000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@e0122000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0122000 0x0 0x2000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: serial@e0124000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0124000 0x0 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: serial@e0126000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@e0128000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0128000 0x0 0x2000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart5: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart6: serial@e012c000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012c000 0x0 0x2000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
timer: timer@e0228000 {
compatible = "actions,s900-timer";
reg = <0x0 0xe0228000 0x0 0x8000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "timer1";
};
};
};

5
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -1,6 +1,11 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

15
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View File

@ -67,6 +67,14 @@ reg_vcc3v3: vcc3v3 {
};
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -77,6 +85,13 @@ &i2c1_pins {
bias-pull-up;
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;

95
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts Normal file
View File

@ -0,0 +1,95 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi Win/Win Plus";
compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&ehci1 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
status = "okay";
};

17
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
View File

@ -46,5 +46,20 @@ / {
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
/* TODO: Camera, touchscreen, etc. */
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};

57
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View File

@ -52,6 +52,10 @@ / {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
@ -66,10 +70,23 @@ reg_vcc3v3: vcc3v3 {
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins>;
phy-mode = "rmii";
phy-handle = <&ext_rmii_phy1>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -80,6 +97,13 @@ &i2c1_pins {
bias-pull-up;
};
&mdio {
ext_rmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -91,16 +115,49 @@ &mmc0 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
/* On Wifi/BT connector, with RTS/CTS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "disabled";
};
/* On Pi-2 connector */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
/* On Euler connector */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
/* On Euler connector, RTS/CTS optional */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "disabled";
};
&usb_otg {
dr_mode = "host";
status = "okay";

126
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts Normal file
View File

@ -0,0 +1,126 @@
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun50i-a64-pine64.dts, which is:
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64-sopine.dtsi"
/ {
model = "SoPine with baseboard";
compatible = "pine64,sopine-baseboard", "pine64,sopine",
"allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
status = "okay";
};

65
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi Normal file
View File

@ -0,0 +1,65 @@
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun50i-a64-pine64.dts, which is:
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun50i-a64.dtsi"
/ {
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
non-removable;
disable-wp;
bus-width = <4>;
status = "okay";
};

137
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -43,6 +43,7 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
@ -129,6 +130,12 @@ soc {
#size-cells = <1>;
ranges;
syscon: syscon@1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
reg = <0x01c00000 0x1000>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@ -204,6 +211,28 @@ usbphy: phy@01c19400 {
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
status = "disabled";
};
ohci0: usb@01c1a400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
status = "disabled";
};
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
@ -281,6 +310,21 @@ mmc2_pins: mmc2-pins {
bias-pull-up;
};
rmii_pins: rmii_pins {
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
function = "emac";
drive-strength = <40>;
};
rgmii_pins: rgmii_pins {
pins = "PD8", "PD9", "PD10", "PD11", "PD12",
"PD13", "PD15", "PD16", "PD17", "PD18",
"PD19", "PD20", "PD21", "PD22", "PD23";
function = "emac";
drive-strength = <40>;
};
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
@ -295,6 +339,26 @@ uart1_rts_cts_pins: uart1_rts_cts_pins {
pins = "PG8", "PG9";
function = "uart1";
};
uart2_pins: uart2-pins {
pins = "PB0", "PB1";
function = "uart2";
};
uart3_pins: uart3-pins {
pins = "PD0", "PD1";
function = "uart3";
};
uart4_pins: uart4-pins {
pins = "PD2", "PD3";
function = "uart4";
};
uart4_rts_cts_pins: uart4-rts-cts-pins {
pins = "PD4", "PD5";
function = "uart4";
};
};
uart0: serial@1c28000 {
@ -303,8 +367,8 @@ uart0: serial@1c28000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 67>;
resets = <&ccu 46>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@ -314,8 +378,8 @@ uart1: serial@1c28400 {
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 68>;
resets = <&ccu 47>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@ -325,8 +389,8 @@ uart2: serial@1c28800 {
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 69>;
resets = <&ccu 48>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@ -336,8 +400,8 @@ uart3: serial@1c28c00 {
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 70>;
resets = <&ccu 49>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
@ -347,8 +411,8 @@ uart4: serial@1c29000 {
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu 71>;
resets = <&ccu 50>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
@ -356,8 +420,8 @@ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 63>;
resets = <&ccu 42>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -367,8 +431,8 @@ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 64>;
resets = <&ccu 43>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -378,13 +442,33 @@ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 65>;
resets = <&ccu 44>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
@ -417,12 +501,31 @@ r_pio: pinctrl@01f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
r_rsb_pins: rsb@0 {
pins = "PL0", "PL1";
function = "s_rsb";
};
};
r_rsb: rsb@1f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu 6>;
clock-frequency = <3000000>;
resets = <&r_ccu 2>;
pinctrl-names = "default";
pinctrl-0 = <&r_rsb_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};

161
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts Normal file
View File

@ -0,0 +1,161 @@
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "FriendlyARM NanoPi NEO 2";
compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr {
label = "nanopi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
status {
label = "nanopi:blue:status";
gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
status = "okay";
};
};
&ehci0 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
/* USB Type-A port's VBUS is always on */
usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};

27
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
View File

@ -59,6 +59,7 @@ reg_vcc3v3: vcc3v3 {
};
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -91,6 +92,16 @@ sw4 {
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
@ -126,12 +137,28 @@ &ehci3 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

232
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts Normal file
View File

@ -0,0 +1,232 @@
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on sun50i-h5-orangepi-pc2.dts, which is:
* Copyright (C) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Xunlong Orange Pi Prime";
compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr {
label = "orangepi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
status {
label = "orangepi:red:status";
gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
};
};
r-gpio-keys {
compatible = "gpio-keys";
sw4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
};
};
&codec {
allwinner,audio-routing =
"Line Out", "LINEOUT",
"MIC1", "Mic",
"Mic", "MBIAS";
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
/* USB Type-A ports' VBUS is always on */
usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};

92
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts Normal file
View File

@ -0,0 +1,92 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi Zero Plus2";
compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};

9
arch/arm64/boot/dts/amlogic/Makefile
View File

@ -1,3 +1,4 @@
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
@ -7,15 +8,17 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

60
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@ -121,19 +121,42 @@ hdmi_connector_in: endpoint {
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@ -154,7 +177,7 @@ &sd_emmc_a {
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@ -198,32 +221,9 @@ &sd_emmc_c {
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&ethmac {
status = "okay";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

11
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -200,7 +200,7 @@ scpi_dvfs: scpi_clocks@0 {
};
scpi_sensors: sensors {
compatible = "arm,scpi-sensors";
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
@ -304,6 +304,15 @@ i2c_C: i2c@87e0 {
status = "disabled";
};
spicc: spi@8d80 {
compatible = "amlogic,meson-gx-spicc";
reg = <0x0 0x08d80 0x0 0x80>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;

291
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts Normal file
View File

@ -0,0 +1,291 @@
/*
* Copyright (c) 2017 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
stat {
label = "nanopi-k2:blue:stat";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
default-state = "on";
panic-indicator;
};
};
vdd_5v: regulator-vdd-5v {
compatible = "regulator-fixed";
regulator-name = "VDD_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddio_ao3v3: regulator-vddio-ao3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vddio_tf: regulator-vddio-tf {
compatible = "regulator-gpio";
regulator-name = "VDDIO_TF";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0>,
<1800000 1>;
};
wifi_32k: wifi-32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi_32k>;
clock-names = "ext_clock";
};
vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* SDIO */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddio_ao3v3>;
vqmmc-supply = <&vddio_ao18>;
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
/* SD */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddio_ao3v3>;
vqmmc-supply = <&vddio_tf>;
};
/* eMMC */
&sd_emmc_c {
status = "disabled";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc3v3>;
vqmmc-supply = <&vcc1v8>;
};
/* DBG_UART */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
/* Bluetooth on AP6212 */
&uart_A {
status = "disabled";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
};
/* 40-pin CON1 */
&uart_C {
status = "disabled";
pinctrl-0 = <&uart_c_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&vdd_5v>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

52
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
View File

@ -165,10 +165,10 @@ hdmi_connector_in: endpoint {
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
@ -195,12 +195,32 @@ eth_phy0: ethernet-phy@0 {
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@ -260,28 +280,8 @@ &sd_emmc_c {
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
&uart_AO {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

108
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -137,16 +137,6 @@ emmc_pwrseq: emmc-pwrseq {
};
};
&scpi_clocks {
status = "disabled";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
@ -172,6 +162,33 @@ eth_phy0: ethernet-phy@0 {
};
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pinctrl_aobus {
gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
"USB HUB nRESET", "USB OTG Power En",
@ -223,55 +240,15 @@ &pinctrl_periphs {
"";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8>;
};
&scpi_clocks {
status = "disabled";
};
/* SD */
&sd_emmc_b {
status = "okay";
@ -309,3 +286,26 @@ &sd_emmc_c {
vmmc-supply = <&vcc3v3>;
vqmmc-supply = <&vcc1v8>;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

78
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View File

@ -126,7 +126,7 @@ sdio_pwrseq: sdio-pwrseq {
clock-names = "ext_clock";
};
cvbs-connector {
cvbs_connector: cvbs-connector {
compatible = "composite-video-connector";
port {
@ -148,34 +148,36 @@ hdmi_connector_in: endpoint {
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
@ -198,7 +200,7 @@ &sd_emmc_a {
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@ -242,28 +244,26 @@ &sd_emmc_c {
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

56
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View File

@ -111,18 +111,6 @@ sdio_pwrseq: sdio-pwrseq {
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
@ -149,21 +137,18 @@ eth_phy0: ethernet-phy@0 {
};
};
&usb0_phy {
&ir {
status = "okay";
phy-supply = <&usb_vbus>;
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
@ -186,7 +171,7 @@ &sd_emmc_a {
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
@ -229,10 +214,25 @@ &sd_emmc_c {
vmmcq-sumpply = <&vcc_1v8>;
};
&pwm_ef {
&uart_AO {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_vbus>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

6
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
View File

@ -59,10 +59,10 @@ system {
panic-indicator;
};
};
};
cvbs-connector {
status = "disabled";
};
&cvbs_connector {
status = "disabled";
};
&ethmac {

40
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
View File

@ -85,6 +85,34 @@ button@0 {
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
};
};
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
@ -113,6 +141,18 @@ eth_phy0: ethernet-phy@0 {
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;

220
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -97,13 +97,6 @@ usb1: usb@c9100000 {
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
};
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
@ -249,9 +242,119 @@ mux {
function = "spdif_out_ao";
};
};
ao_cec_pins: ao_cec {
mux {
groups = "ao_cec";
function = "cec_ao";
};
};
ee_cec_pins: ee_cec {
mux {
groups = "ee_cec";
function = "cec_ao";
};
};
};
};
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&hwrng {
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
@ -262,7 +365,7 @@ pinctrl_periphs: pinctrl@4b0 {
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
@ -290,6 +393,22 @@ mux {
};
};
spi_pins: spi {
mux {
groups = "spi_miso",
"spi_mosi",
"spi_sclk";
function = "spi";
};
};
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
function = "spi";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@ -521,67 +640,6 @@ mux {
};
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
@ -613,6 +671,13 @@ &sd_emmc_c {
clock-names = "core", "clkin0", "clkin1";
};
&spicc {
clocks = <&clkc CLKID_SPICC>;
clock-names = "core";
resets = <&reset RESET_PERIPHS_SPICC>;
num-cs = <1>;
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
@ -620,20 +685,3 @@ &spifc {
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
&hwrng {
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

24
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
View File

@ -84,6 +84,17 @@ vddio_ao18: regulator-vddio_ao18 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
/* P230 has exclusive choice between internal or external PHY */
@ -113,6 +124,19 @@ external_phy: ethernet-phy@0 {
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;

25
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
View File

@ -54,6 +54,29 @@ power {
linux,default-trigger = "default-on";
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&i2c_A {
@ -95,7 +118,7 @@ &pwm_ef {
};
&sd_emmc_a {
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};

92
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts Normal file
View File

@ -0,0 +1,92 @@
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Author: Jerome Brunet <jbrunet@baylibre.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x-p212.dtsi"
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Technology CC";
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
leds {
compatible = "gpio-leds";
system {
label = "librecomputer:system-status";
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
default-state = "on";
panic-indicator;
};
blue {
label = "librecomputer:blue";
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
/*
* The following devices exists but are exposed on the general
* purpose GPIO header. End user may well decide to use those pins
* for another purpose
*/
&sd_emmc_a {
status = "disabled";
};
&uart_A {
status = "disabled";
};
&wifi32k {
status = "disabled";
};

52
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
View File

@ -140,10 +140,10 @@ hdmi_connector_in: endpoint {
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
@ -152,12 +152,32 @@ &ethmac {
phy-handle = <&internal_phy>;
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
@ -217,28 +237,8 @@ &sd_emmc_c {
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
&uart_AO {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

23
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
View File

@ -58,6 +58,17 @@ cvbs_connector_in: endpoint {
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&cvbs_vdac_port {
@ -66,6 +77,18 @@ cvbs_vdac_out: endpoint {
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
View File

@ -48,7 +48,7 @@ / {
compatible = "amlogic,s905x", "amlogic,meson-gxl";
};
/* S905X Only has access to its internal PHY */
/* S905X only has access to its internal PHY */
&ethmac {
phy-mode = "rmii";
phy-handle = <&internal_phy>;

127
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -190,9 +190,59 @@ mux {
function = "spdif_out_ao";
};
};
ao_cec_pins: ao_cec {
mux {
groups = "ao_cec";
function = "cec_ao";
};
};
ee_cec_pins: ee_cec {
mux {
groups = "ee_cec";
function = "cec_ao";
};
};
};
};
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxl-periphs-pinctrl";
@ -203,12 +253,12 @@ pinctrl_periphs: pinctrl@4b0 {
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 101>;
gpio-ranges = <&pinctrl_periphs 0 10 101>;
};
emmc_pins: emmc {
@ -231,6 +281,22 @@ mux {
};
};
spi_pins: spi {
mux {
groups = "spi_miso",
"spi_mosi",
"spi_sclk";
function = "spi";
};
};
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
function = "spi";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@ -354,6 +420,20 @@ mux {
};
};
eth_link_led_pins: eth_link_led {
mux {
groups = "eth_link_led";
function = "eth_led";
};
};
eth_act_led_pins: eth_act_led {
mux {
groups = "eth_act_led";
function = "eth_led";
};
};
pwm_a_pins: pwm_a {
mux {
groups = "pwm_a";
@ -501,30 +581,6 @@ external_mdio: mdio@2009087f {
};
};
&hiubus {
clkc: clock-controller@0 {
compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
&i2c_C {
clocks = <&clkc CLKID_I2C>;
};
&saradc {
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
@ -556,6 +612,13 @@ &sd_emmc_c {
clock-names = "core", "clkin0", "clkin1";
};
&spicc {
clocks = <&clkc CLKID_SPICC>;
clock-names = "core";
resets = <&reset RESET_PERIPHS_SPICC>;
num-cs = <1>;
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
@ -563,15 +626,3 @@ &spifc {
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

87
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
View File

@ -113,11 +113,49 @@ hdmi_connector_in: endpoint {
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
@ -164,47 +202,8 @@ &sd_emmc_c {
vqmmc-supply = <&vddio_boot>;
};
&ethmac {
&uart_AO {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

240
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts Normal file
View File

@ -0,0 +1,240 @@
/*
* Copyright (c) 2016-2017 Andreas Färber
*
* Based on nexbox-a1:
*
* Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxm.dtsi"
/ {
compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
model = "R-Box Pro";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
};
leds {
compatible = "gpio-leds";
blue {
label = "rbox-pro:blue:on";
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
red {
label = "rbox-pro:red:standby";
gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
default-state = "off";
retain-state-suspended;
panic-indicator;
};
};
vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
amlogic,tx-delay-ns = <2>;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: brcmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

58
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -53,7 +53,6 @@ smmu_etr: iommu@2b600000 {
#global-interrupts = <1>;
dma-coherent;
power-domains = <&scpi_devpd 0>;
status = "disabled";
};
gic: interrupt-controller@2c010000 {
@ -202,6 +201,15 @@ stm_out_port: endpoint {
};
};
cpu_debug0: cpu_debug@22010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22010000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>;
@ -252,6 +260,15 @@ cluster0_funnel_in_port1: endpoint {
};
};
cpu_debug1: cpu_debug@22110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22110000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm1: etm@22140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22140000 0 0x1000>;
@ -266,6 +283,15 @@ cluster0_etm1_out_port: endpoint {
};
};
cpu_debug2: cpu_debug@23010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23010000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm2: etm@23040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23040000 0 0x1000>;
@ -330,6 +356,15 @@ cluster1_funnel_in_port3: endpoint {
};
};
cpu_debug3: cpu_debug@23110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23110000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm3: etm@23140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23140000 0 0x1000>;
@ -344,6 +379,15 @@ cluster1_etm1_out_port: endpoint {
};
};
cpu_debug4: cpu_debug@23210000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23210000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm4: etm@23240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23240000 0 0x1000>;
@ -358,6 +402,15 @@ cluster1_etm2_out_port: endpoint {
};
};
cpu_debug5: cpu_debug@23310000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23310000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm5: etm@23340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23340000 0 0x1000>;
@ -546,7 +599,6 @@ smmu_hdlcd1: iommu@7fb10000 {
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
status = "disabled";
};
smmu_hdlcd0: iommu@7fb20000 {
@ -556,7 +608,6 @@ smmu_hdlcd0: iommu@7fb20000 {
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
status = "disabled";
};
smmu_usb: iommu@7fb30000 {
@ -567,7 +618,6 @@ smmu_usb: iommu@7fb30000 {
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
status = "disabled";
};
dma@7ff00000 {

24
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -281,3 +281,27 @@ &replicator_in_port0 {
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
&cpu_debug0 {
cpu = <&A57_0>;
};
&cpu_debug1 {
cpu = <&A57_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};

24
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -281,3 +281,27 @@ &replicator_in_port0 {
&stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>;
};
&cpu_debug0 {
cpu = <&A72_0>;
};
&cpu_debug1 {
cpu = <&A72_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};

24
arch/arm64/boot/dts/arm/juno.dts
View File

@ -268,3 +268,27 @@ main_funnel_in_port2: endpoint {
};
};
};
&cpu_debug0 {
cpu = <&A57_0>;
};
&cpu_debug1 {
cpu = <&A57_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};

1
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
dts-dirs := stingray
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

17
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
View File

@ -22,3 +22,20 @@ act {
&uart1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};

4
arch/arm64/boot/dts/broadcom/bcm2837.dtsi
View File

@ -75,6 +75,10 @@ &intc {
interrupts = <8>;
};
&cpu_thermal {
coefficients = <(-538) 412000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2837-thermal";

14
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -460,6 +460,20 @@ pmu@9000 {
};
};
usbdrd_phy: phy@66000960 {
#phy-cells = <0>;
compatible = "brcm,ns2-drd-phy";
reg = <0x66000960 0x24>,
<0x67012800 0x4>,
<0x6501d148 0x4>,
<0x664d0700 0x4>;
reg-names = "icfg", "rst-ctrl",
"crmu-ctrl", "usb2-strap";
id-gpios = <&gpio_g 30 0>;
vbus-gpios = <&gpio_g 31 0>;
status = "disabled";
};
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;

6
arch/arm64/boot/dts/broadcom/stingray/Makefile Normal file
View File

@ -0,0 +1,6 @@
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

131
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi Normal file
View File

@ -0,0 +1,131 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stingray.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart1;
serial1 = &uart0;
serial2 = &uart2;
serial3 = &uart3;
};
sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio0_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 18 0>;
states = <3300000 0x0
1800000 0x1>;
};
sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio1_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 19 0>;
states = <3300000 0x0
1800000 0x1>;
};
};
&memory { /* Default DRAM banks */
reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
&uart1 {
status = "okay";
};
&pwm {
status = "okay";
};
&i2c0 {
status = "okay";
pca9505: pca9505@20 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
&i2c1 {
status = "okay";
pcf8574: pcf8574@20 {
compatible = "nxp,pcf8574a";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
};
};
&nand {
status = "ok";
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&sdio0 {
vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
non-removable;
full-pwr-cycle;
status = "okay";
};
&sdio1 {
vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
full-pwr-cycle;
status = "okay";
};

78
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts Normal file
View File

@ -0,0 +1,78 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742k", "brcm,stingray";
model = "Stingray Combo SVK (BCM958742K)";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&ssp0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 34 0>;
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&ssp1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 96 0>;
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

40
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts Normal file
View File

@ -0,0 +1,40 @@
/*
* BSD LICENSE
*
* Copyright(c) 2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742t", "brcm,stingray";
model = "Stingray SST100 (BCM958742T)";
};

170
arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi Normal file
View File

@ -0,0 +1,170 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-sr.h>
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
crmu_ref25m: crmu_ref25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&osc>;
clock-div = <2>;
clock-mult = <1>;
};
genpll0: genpll0@0001d104 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll0";
reg = <0x0001d104 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll0", "clk_125", "clk_scr",
"clk_250", "clk_pcie_axi",
"clk_paxc_axi_x2",
"clk_paxc_axi";
};
genpll3: genpll3@0001d1e0 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll3";
reg = <0x0001d1e0 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll3", "clk_hsls",
"clk_sdio";
};
genpll4: genpll4@0001d214 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll4";
reg = <0x0001d214 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll4", "clk_ccn",
"clk_tpiu_pll", "noc_clk",
"pll_chclk_fs4",
"clk_bridge_fscpu";
};
genpll5: genpll5@0001d248 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll5";
reg = <0x0001d248 0x32>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "genpll5", "fs4_hf_clk",
"crypto_ae_clk", "raid_ae_clk";
};
lcpll0: lcpll0@0001d0c4 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll0";
reg = <0x0001d0c4 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll0", "clk_sata_refp",
"clk_sata_refn", "clk_sata_350",
"clk_sata_500";
};
lcpll1: lcpll1@0001d138 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll1";
reg = <0x0001d138 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll1", "clk_wanpn",
"clk_usb_ref",
"timesync_evt_clk";
};
hsls_clk: hsls_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 1>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_div2_clk: hsls_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
hsls_div4_clk: hsls_div4_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
hsls_25m_clk: hsls_25m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&crmu_ref25m>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_25m_div2_clk: hsls_25m_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hsls_25m_clk>;
clock-div = <2>;
clock-mult = <1>;
};
sdio0_clk: sdio0_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};
sdio1_clk: sdio1_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};

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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
pinconf: pinconf@00140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
/* pinconf functions */
};
pinmux: pinmux@0014029c {
compatible = "pinctrl-single";
reg = <0x0014029c 0x250>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = <
&range 0 154 MODE_GPIO
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
/* pinctrl functions */
tsio_pins: pinmux_gpio_14 {
pinctrl-single,pins = <
0x038 MODE_NITRO /* tsio_0 */
0x03c MODE_NITRO /* tsio_1 */
>;
};
nor_pins: pinmux_pnor_adv_n {
pinctrl-single,pins = <
0x0ac MODE_PNOR /* nand_ce1_n */
0x0b0 MODE_PNOR /* nand_ce0_n */
0x0b4 MODE_PNOR /* nand_we_n */
0x0b8 MODE_PNOR /* nand_wp_n */
0x0bc MODE_PNOR /* nand_re_n */
0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
0x0c4 MODE_PNOR /* nand_io0_0 */
0x0c8 MODE_PNOR /* nand_io1_0 */
0x0cc MODE_PNOR /* nand_io2_0 */
0x0d0 MODE_PNOR /* nand_io3_0 */
0x0d4 MODE_PNOR /* nand_io4_0 */
0x0d8 MODE_PNOR /* nand_io5_0 */
0x0dc MODE_PNOR /* nand_io6_0 */
0x0e0 MODE_PNOR /* nand_io7_0 */
0x0e4 MODE_PNOR /* nand_io8_0 */
0x0e8 MODE_PNOR /* nand_io9_0 */
0x0ec MODE_PNOR /* nand_io10_0 */
0x0f0 MODE_PNOR /* nand_io11_0 */
0x0f4 MODE_PNOR /* nand_io12_0 */
0x0f8 MODE_PNOR /* nand_io13_0 */
0x0fc MODE_PNOR /* nand_io14_0 */
0x100 MODE_PNOR /* nand_io15_0 */
0x104 MODE_PNOR /* nand_ale_0 */
0x108 MODE_PNOR /* nand_cle_0 */
0x040 MODE_PNOR /* pnor_adv_n */
0x044 MODE_PNOR /* pnor_baa_n */
0x048 MODE_PNOR /* pnor_bls_0_n */
0x04c MODE_PNOR /* pnor_bls_1_n */
0x050 MODE_PNOR /* pnor_cre */
0x054 MODE_PNOR /* pnor_cs_2_n */
0x058 MODE_PNOR /* pnor_cs_1_n */
0x05c MODE_PNOR /* pnor_cs_0_n */
0x060 MODE_PNOR /* pnor_we_n */
0x064 MODE_PNOR /* pnor_oe_n */
0x068 MODE_PNOR /* pnor_intr */
0x06c MODE_PNOR /* pnor_dat_0 */
0x070 MODE_PNOR /* pnor_dat_1 */
0x074 MODE_PNOR /* pnor_dat_2 */
0x078 MODE_PNOR /* pnor_dat_3 */
0x07c MODE_PNOR /* pnor_dat_4 */
0x080 MODE_PNOR /* pnor_dat_5 */
0x084 MODE_PNOR /* pnor_dat_6 */
0x088 MODE_PNOR /* pnor_dat_7 */
0x08c MODE_PNOR /* pnor_dat_8 */
0x090 MODE_PNOR /* pnor_dat_9 */
0x094 MODE_PNOR /* pnor_dat_10 */
0x098 MODE_PNOR /* pnor_dat_11 */
0x09c MODE_PNOR /* pnor_dat_12 */
0x0a0 MODE_PNOR /* pnor_dat_13 */
0x0a4 MODE_PNOR /* pnor_dat_14 */
0x0a8 MODE_PNOR /* pnor_dat_15 */
>;
};
nand_pins: pinmux_nand_ce1_n {
pinctrl-single,pins = <
0x0ac MODE_NAND /* nand_ce1_n */
0x0b0 MODE_NAND /* nand_ce0_n */
0x0b4 MODE_NAND /* nand_we_n */
0x0b8 MODE_NAND /* nand_wp_n */
0x0bc MODE_NAND /* nand_re_n */
0x0c0 MODE_NAND /* nand_rdy_bsy_n */
0x0c4 MODE_NAND /* nand_io0_0 */
0x0c8 MODE_NAND /* nand_io1_0 */
0x0cc MODE_NAND /* nand_io2_0 */
0x0d0 MODE_NAND /* nand_io3_0 */
0x0d4 MODE_NAND /* nand_io4_0 */
0x0d8 MODE_NAND /* nand_io5_0 */
0x0dc MODE_NAND /* nand_io6_0 */
0x0e0 MODE_NAND /* nand_io7_0 */
0x0e4 MODE_NAND /* nand_io8_0 */
0x0e8 MODE_NAND /* nand_io9_0 */
0x0ec MODE_NAND /* nand_io10_0 */
0x0f0 MODE_NAND /* nand_io11_0 */
0x0f4 MODE_NAND /* nand_io12_0 */
0x0f8 MODE_NAND /* nand_io13_0 */
0x0fc MODE_NAND /* nand_io14_0 */
0x100 MODE_NAND /* nand_io15_0 */
0x104 MODE_NAND /* nand_ale_0 */
0x108 MODE_NAND /* nand_cle_0 */
>;
};
pwm0_pins: pinmux_pwm_0 {
pinctrl-single,pins = <
0x10c MODE_NITRO
>;
};
pwm1_pins: pinmux_pwm_1 {
pinctrl-single,pins = <
0x110 MODE_NITRO
>;
};
pwm2_pins: pinmux_pwm_2 {
pinctrl-single,pins = <
0x114 MODE_NITRO
>;
};
pwm3_pins: pinmux_pwm_3 {
pinctrl-single,pins = <
0x118 MODE_NITRO
>;
};
dbu_rxd_pins: pinmux_uart1_sin_nitro {
pinctrl-single,pins = <
0x11c MODE_NITRO /* dbu_rxd */
0x120 MODE_NITRO /* dbu_txd */
>;
};
uart1_pins: pinmux_uart1_sin_nand {
pinctrl-single,pins = <
0x11c MODE_NAND /* uart1_sin */
0x120 MODE_NAND /* uart1_out */
>;
};
uart2_pins: pinmux_uart2_sin {
pinctrl-single,pins = <
0x124 MODE_NITRO /* uart2_sin */
0x128 MODE_NITRO /* uart2_out */
>;
};
uart3_pins: pinmux_uart3_sin {
pinctrl-single,pins = <
0x12c MODE_NITRO /* uart3_sin */
0x130 MODE_NITRO /* uart3_out */
>;
};
i2s_pins: pinmux_i2s_bitclk {
pinctrl-single,pins = <
0x134 MODE_NITRO /* i2s_bitclk */
0x138 MODE_NITRO /* i2s_sdout */
0x13c MODE_NITRO /* i2s_sdin */
0x140 MODE_NITRO /* i2s_ws */
0x144 MODE_NITRO /* i2s_mclk */
0x148 MODE_NITRO /* i2s_spdif_out */
>;
};
qspi_pins: pinumx_qspi_hold_n {
pinctrl-single,pins = <
0x14c MODE_NAND /* qspi_hold_n */
0x150 MODE_NAND /* qspi_wp_n */
0x154 MODE_NAND /* qspi_sck */
0x158 MODE_NAND /* qspi_cs_n */
0x15c MODE_NAND /* qspi_mosi */
0x160 MODE_NAND /* qspi_miso */
>;
};
mdio_pins: pinumx_ext_mdio {
pinctrl-single,pins = <
0x164 MODE_NITRO /* ext_mdio */
0x168 MODE_NITRO /* ext_mdc */
>;
};
i2c0_pins: pinmux_i2c0_sda {
pinctrl-single,pins = <
0x16c MODE_NITRO /* i2c0_sda */
0x170 MODE_NITRO /* i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1_sda {
pinctrl-single,pins = <
0x174 MODE_NITRO /* i2c1_sda */
0x178 MODE_NITRO /* i2c1_scl */
>;
};
sdio0_pins: pinmux_sdio0_cd_l {
pinctrl-single,pins = <
0x17c MODE_NITRO /* sdio0_cd_l */
0x180 MODE_NITRO /* sdio0_clk_sdcard */
0x184 MODE_NITRO /* sdio0_data0 */
0x188 MODE_NITRO /* sdio0_data1 */
0x18c MODE_NITRO /* sdio0_data2 */
0x190 MODE_NITRO /* sdio0_data3 */
0x194 MODE_NITRO /* sdio0_data4 */
0x198 MODE_NITRO /* sdio0_data5 */
0x19c MODE_NITRO /* sdio0_data6 */
0x1a0 MODE_NITRO /* sdio0_data7 */
0x1a4 MODE_NITRO /* sdio0_cmd */
0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
0x1ac MODE_NITRO /* sdio0_led_on */
0x1b0 MODE_NITRO /* sdio0_wp */
>;
};
sdio1_pins: pinmux_sdio1_cd_l {
pinctrl-single,pins = <
0x1b4 MODE_NITRO /* sdio1_cd_l */
0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
0x1bc MODE_NITRO /* sdio1_data0 */
0x1c0 MODE_NITRO /* sdio1_data1 */
0x1c4 MODE_NITRO /* sdio1_data2 */
0x1c8 MODE_NITRO /* sdio1_data3 */
0x1cc MODE_NITRO /* sdio1_data4 */
0x1d0 MODE_NITRO /* sdio1_data5 */
0x1d4 MODE_NITRO /* sdio1_data6 */
0x1d8 MODE_NITRO /* sdio1_data7 */
0x1dc MODE_NITRO /* sdio1_cmd */
0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
0x1e4 MODE_NITRO /* sdio1_led_on */
0x1e8 MODE_NITRO /* sdio1_wp */
>;
};
spi0_pins: pinmux_spi0_sck_nand {
pinctrl-single,pins = <
0x1ec MODE_NITRO /* spi0_sck */
0x1f0 MODE_NITRO /* spi0_rxd */
0x1f4 MODE_NITRO /* spi0_fss */
0x1f8 MODE_NITRO /* spi0_txd */
>;
};
spi1_pins: pinmux_spi1_sck_nand {
pinctrl-single,pins = <
0x1fc MODE_NITRO /* spi1_sck */
0x200 MODE_NITRO /* spi1_rxd */
0x204 MODE_NITRO /* spi1_fss */
0x208 MODE_NITRO /* spi1_txd */
>;
};
nuart_pins: pinmux_uart0_sin_nitro {
pinctrl-single,pins = <
0x20c MODE_NITRO /* nuart_rxd */
0x210 MODE_NITRO /* nuart_txd */
>;
};
uart0_pins: pinumux_uart0_sin_nand {
pinctrl-single,pins = <
0x20c MODE_NAND /* uart0_sin */
0x210 MODE_NAND /* uart0_out */
0x214 MODE_NAND /* uart0_rts */
0x218 MODE_NAND /* uart0_cts */
0x21c MODE_NAND /* uart0_dtr */
0x220 MODE_NAND /* uart0_dcd */
0x224 MODE_NAND /* uart0_dsr */
0x228 MODE_NAND /* uart0_ri */
>;
};
drdu2_pins: pinmux_drdu2_overcurrent {
pinctrl-single,pins = <
0x22c MODE_NITRO /* drdu2_overcurrent */
0x230 MODE_NITRO /* drdu2_vbus_ppc */
0x234 MODE_NITRO /* drdu2_vbus_present */
0x238 MODE_NITRO /* drdu2_id */
>;
};
drdu3_pins: pinmux_drdu3_overcurrent {
pinctrl-single,pins = <
0x23c MODE_NITRO /* drdu3_overcurrent */
0x240 MODE_NITRO /* drdu3_vbus_ppc */
0x244 MODE_NITRO /* drdu3_vbus_present */
0x248 MODE_NITRO /* drdu3_id */
>;
};
usb3h_pins: pinmux_usb3h_overcurrent {
pinctrl-single,pins = <
0x24c MODE_NITRO /* usb3h_overcurrent */
0x250 MODE_NITRO /* usb3h_vbus_ppc */
>;
};
};

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/*
* BSD LICENSE
*
* Copyright(c) 2015-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,stingray";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x201>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x301>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
CLUSTER0_L2: l2-cache@000 {
compatible = "cache";
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
};
};
memory: memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
scr {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
gic: interrupt-controller@02c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
reg = <0x02c00000 0x010000>, /* GICD */
<0x02e00000 0x600000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@63c20000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x02c20000 0x10000>;
};
};
smmu: mmu@03000000 {
compatible = "arm,mmu-500";
reg = <0x03000000 0x80000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <2>;
};
};
crmu: crmu {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x66400000 0x100000>;
#include "stingray-clock.dtsi"
gpio_crmu: gpio@00024800 {
compatible = "brcm,iproc-gpio";
reg = <0x00024800 0x4c>;
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
};
};
hsls {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x68900000 0x17700000>;
#include "stingray-pinctrl.dtsi"
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
clocks = <&crmu_ref25m>;
#pwm-cells = <3>;
status = "disabled";
};
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
wdt0: watchdog@000c0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x000c0000 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdogclk", "apb_pclk";
};
gpio_hsls: gpio@000d0000 {
compatible = "brcm,iproc-gpio";
reg = <0x000d0000 0x864>;
ngpios = <151>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinmux 0 0 16>,
<&pinmux 16 71 2>,
<&pinmux 18 131 8>,
<&pinmux 26 83 6>,
<&pinmux 32 123 4>,
<&pinmux 36 43 24>,
<&pinmux 60 89 2>,
<&pinmux 62 73 4>,
<&pinmux 66 95 28>,
<&pinmux 94 127 4>,
<&pinmux 98 139 10>,
<&pinmux 108 16 27>,
<&pinmux 135 77 6>,
<&pinmux 141 67 4>,
<&pinmux 145 149 6>,
<&pinmux 151 91 4>;
};
i2c1: i2c@000e0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000e0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: uart@00100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: uart@00110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: uart@00120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: uart@00130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ssp0: ssp@00180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00180000 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "spiclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssp1: ssp@00190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00190000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "spiclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hwrng: hwrng@00220000 {
compatible = "brcm,iproc-rng200";
reg = <0x00220000 0x28>;
};
dma0: dma@00310000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x00310000 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&hsls_div2_clk>;
clock-names = "apb_pclk";
iommus = <&smmu 0x6000 0x0000>;
};
nand: nand@00360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
<0x0050a408 0x600>,
<0x00360f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
status = "disabled";
};
sdio0: sdhci@003f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio0_clk>;
iommus = <&smmu 0x6002 0x0000>;
status = "disabled";
};
sdio1: sdhci@003f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio1_clk>;
iommus = <&smmu 0x6003 0x0000>;
status = "disabled";
};
};
};

1
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
View File

@ -60,7 +60,6 @@ panel@0 {
vci-supply = <&ldo28_reg>;
reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
};
};

2
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A Freedom Board.
*
* Copyright 2016, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual

10
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A QDS Board.
*
* Copyright 2016, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@ -97,6 +97,14 @@ &duart0 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";

15
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS1012A RDB Board.
*
* Copyright 2016, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@ -54,6 +54,19 @@ &duart0 {
status = "okay";
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
status = "okay";
};
&i2c0 {
status = "okay";
};

39
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
*
* Copyright 2016, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
@ -76,10 +76,17 @@ cpu0: cpu@0 {
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-frequency = <125000000>;
clock-output-names = "sysclk";
};
coreclk: coreclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "coreclk";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
@ -117,12 +124,37 @@ soc {
#size-cells = <2>;
ranges;
esdhc0: esdhc@1560000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <0 62 0x4>;
clocks = <&clockgen 4 0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
status = "disabled";
};
scfg: scfg@1570000 {
compatible = "fsl,ls1012a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
};
esdhc1: esdhc@1580000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1580000 0x0 0x10000>;
interrupts = <0 65 0x4>;
clocks = <&clockgen 4 0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
big-endian;
broken-cd;
bus-width = <4>;
status = "disabled";
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
@ -223,7 +255,8 @@ clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
clocks = <&sysclk &coreclk>;
clock-names = "sysclk", "coreclk";
};
tmu: tmu@1f00000 {

45
arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi Normal file
View File

@ -0,0 +1,45 @@
/*
* QorIQ FMan v3 device tree nodes for ls1043
*
* Copyright 2015-2016 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
&soc {
/* include used FMan blocks */
#include "qoriq-fman3-0.dtsi"
#include "qoriq-fman3-0-1g-0.dtsi"
#include "qoriq-fman3-0-1g-1.dtsi"
#include "qoriq-fman3-0-1g-2.dtsi"
#include "qoriq-fman3-0-1g-3.dtsi"
#include "qoriq-fman3-0-1g-4.dtsi"
#include "qoriq-fman3-0-1g-5.dtsi"
#include "qoriq-fman3-0-10g-0.dtsi"
};
&fman0 {
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@ea000 {
};
enet6: ethernet@f0000 {
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015, Freescale Semiconductor
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@ -181,3 +181,5 @@ qflash0: s25fl128s@0 {
reg = <0>;
};
};
#include "fsl-ls1043-post.dtsi"

79
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015, Freescale Semiconductor
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@ -75,11 +75,11 @@ adt7461a@4c {
reg = <0x4c>;
};
eeprom@52 {
compatible = "at24,24c512";
compatible = "atmel,24c512";
reg = <0x52>;
};
eeprom@53 {
compatible = "at24,24c512";
compatible = "atmel,24c512";
reg = <0x53>;
};
rtc@68 {
@ -139,3 +139,76 @@ &duart0 {
&duart1 {
status = "okay";
};
#include "fsl-ls1043-post.dtsi"
&fman0 {
ethernet@e0000 {
phy-handle = <&qsgmii_phy1>;
phy-connection-type = "qsgmii";
};
ethernet@e2000 {
phy-handle = <&qsgmii_phy2>;
phy-connection-type = "qsgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-txid";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii-txid";
};
ethernet@e8000 {
phy-handle = <&qsgmii_phy3>;
phy-connection-type = "qsgmii";
};
ethernet@ea000 {
phy-handle = <&qsgmii_phy4>;
phy-connection-type = "qsgmii";
};
ethernet@f0000 { /* 10GEC1 */
phy-handle = <&aqr105_phy>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
qsgmii_phy1: ethernet-phy@4 {
reg = <0x4>;
};
qsgmii_phy2: ethernet-phy@5 {
reg = <0x5>;
};
qsgmii_phy3: ethernet-phy@6 {
reg = <0x6>;
};
qsgmii_phy4: ethernet-phy@7 {
reg = <0x7>;
};
};
mdio@fd000 {
aqr105_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 132 4>;
reg = <0x1>;
};
};
};

69
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015, Freescale Semiconductor
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
@ -45,6 +45,7 @@
*/
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1043a";
@ -52,6 +53,17 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
fman0 = &fman0;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -106,6 +118,33 @@ memory@80000000 {
/* DRAM space 1, size: 2GiB DRAM */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
compatible = "shared-dma-pool";
size = <0 0x1000000>;
alignment = <0 0x1000000>;
no-map;
};
qman_fqd: qman-fqd {
compatible = "shared-dma-pool";
size = <0 0x400000>;
alignment = <0 0x400000>;
no-map;
};
qman_pfdr: qman-pfdr {
compatible = "shared-dma-pool";
size = <0 0x2000000>;
alignment = <0 0x2000000>;
no-map;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -152,7 +191,7 @@ gic: interrupt-controller@1400000 {
interrupts = <1 9 0xf08>;
};
soc {
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -223,6 +262,7 @@ dcfg: dcfg@1ee0000 {
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
big-endian;
interrupts = <0 43 0x4>;
};
@ -333,6 +373,28 @@ map0 {
};
};
qman: qman@1880000 {
compatible = "fsl,qman";
reg = <0x0 0x1880000 0x0 0x10000>;
interrupts = <0 45 0x4>;
memory-region = <&qman_fqd &qman_pfdr>;
};
bman: bman@1890000 {
compatible = "fsl,bman";
reg = <0x0 0x1890000 0x0 0x10000>;
interrupts = <0 45 0x4>;
memory-region = <&bman_fbpr>;
};
bportals: bman-portals@508000000 {
ranges = <0x0 0x5 0x08000000 0x8000000>;
};
qportals: qman-portals@500000000 {
ranges = <0x0 0x5 0x00000000 0x8000000>;
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@ -688,3 +750,6 @@ pcie@3600000 {
};
};
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"

48
arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi Normal file
View File

@ -0,0 +1,48 @@
/*
* QorIQ FMan v3 device tree nodes for ls1046
*
* Copyright 2015-2016 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
&soc {
/* include used FMan blocks */
#include "qoriq-fman3-0.dtsi"
#include "qoriq-fman3-0-1g-0.dtsi"
#include "qoriq-fman3-0-1g-1.dtsi"
#include "qoriq-fman3-0-1g-2.dtsi"
#include "qoriq-fman3-0-1g-3.dtsi"
#include "qoriq-fman3-0-1g-4.dtsi"
#include "qoriq-fman3-0-1g-5.dtsi"
#include "qoriq-fman3-0-10g-0.dtsi"
#include "qoriq-fman3-0-10g-1.dtsi"
};
&fman0 {
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@ea000 {
};
enet6: ethernet@f0000 {
};
enet7: ethernet@f2000 {
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
* Copyright 2016 Freescale Semiconductor, Inc.
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*
@ -210,3 +210,5 @@ qflash0: s25fl128s@0 {
reg = <0>;
};
};
#include "fsl-ls1046-post.dtsi"

70
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
* Copyright 2016 Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
@ -72,6 +72,14 @@ &duart1 {
status = "okay";
};
&esdhc {
mmc-hs200-1_8v;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
};
&i2c0 {
status = "okay";
@ -148,3 +156,63 @@ qflash1: s25fs512s@1 {
reg = <1>;
};
};
#include "fsl-ls1046-post.dtsi"
&fman0 {
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&sgmii_phy1>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
};
ethernet@f0000 { /* 10GEC1 */
phy-handle = <&aqr106_phy>;
phy-connection-type = "xgmii";
};
ethernet@f2000 { /* 10GEC2 */
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sgmii_phy1: ethernet-phy@3 {
reg = <0x3>;
};
sgmii_phy2: ethernet-phy@4 {
reg = <0x4>;
};
};
mdio@fd000 {
aqr106_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 131 4>;
reg = <0x0>;
};
};
};

75
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016, Freescale Semiconductor, Inc.
* Copyright 2016 Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
@ -55,6 +55,15 @@ / {
aliases {
crypto = &crypto;
fman0 = &fman0;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
};
cpus {
@ -174,7 +183,7 @@ gic: interrupt-controller@1400000 {
IRQ_TYPE_LEVEL_LOW)>;
};
soc {
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@ -190,6 +199,7 @@ ddr: memory-controller@1080000 {
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
big-endian;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
@ -209,10 +219,10 @@ qspi: quadspi@1550000 {
};
esdhc: esdhc@1560000 {
compatible = "fsl,esdhc";
compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>;
clocks = <&clockgen 2 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
big-endian;
@ -268,6 +278,30 @@ sec_jr3: jr@40000 {
};
};
qman: qman@1880000 {
compatible = "fsl,qman";
reg = <0x0 0x1880000 0x0 0x10000>;
interrupts = <0 45 0x4>;
memory-region = <&qman_fqd &qman_pfdr>;
};
bman: bman@1890000 {
compatible = "fsl,bman";
reg = <0x0 0x1890000 0x0 0x10000>;
interrupts = <0 45 0x4>;
memory-region = <&bman_fbpr>;
};
qportals: qman-portals@500000000 {
ranges = <0x0 0x5 0x00000000 0x8000000>;
};
bportals: bman-portals@508000000 {
ranges = <0x0 0x5 0x08000000 0x8000000>;
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x10000>;
@ -567,6 +601,7 @@ usb0: usb@2f00000 {
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb@3000000 {
@ -575,6 +610,7 @@ usb1: usb@3000000 {
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb2: usb@3100000 {
@ -583,6 +619,7 @@ usb2: usb@3100000 {
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
sata: sata@3200000 {
@ -594,4 +631,34 @@ sata: sata@3200000 {
clocks = <&clockgen 4 1>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
compatible = "shared-dma-pool";
size = <0 0x1000000>;
alignment = <0 0x1000000>;
no-map;
};
qman_fqd: qman-fqd {
compatible = "shared-dma-pool";
size = <0 0x800000>;
alignment = <0 0x800000>;
no-map;
};
qman_pfdr: qman-pfdr {
compatible = "shared-dma-pool";
size = <0 0x2000000>;
alignment = <0 0x2000000>;
no-map;
};
};
};
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"

28
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
View File

@ -110,6 +110,30 @@ eeprom@57 {
};
};
&ifc {
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
status = "okay";
nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
fpga: board-control@3,0 {
compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
reg = <0x3 0x0 0x0000100>;
};
};
&duart0 {
status = "okay";
};
@ -118,6 +142,10 @@ &duart1 {
status = "okay";
};
&esdhc {
status = "okay";
};
&sata {
status = "okay";
};

20
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View File

@ -94,6 +94,22 @@ rtc@51 {
};
};
&ifc {
ranges = <0 0 0x5 0x30000000 0x00010000
2 0 0x5 0x20000000 0x00010000>;
status = "okay";
nand@0,0 {
compatible = "fsl,ifc-nand";
reg = <0x0 0x0 0x10000>;
};
fpga: board-control@2,0 {
compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
};
&duart0 {
status = "okay";
};
@ -102,6 +118,10 @@ &duart1 {
status = "okay";
};
&esdhc {
status = "okay";
};
&sata {
status = "okay";
};

111
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -44,6 +44,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1088a";
@ -61,6 +62,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen 1 0>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -89,6 +91,7 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
reg = <0x100>;
clocks = <&clockgen 1 1>;
#cooling-cells = <2>;
};
cpu5: cpu@101 {
@ -153,6 +156,91 @@ clockgen: clocking@1300000 {
clocks = <&sysclk>;
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
<0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
/* Calibration data group 2 */
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
/* Calibration data group 3 */
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
/* Calibration data group 4 */
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
little-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
@ -216,10 +304,6 @@ ifc: ifc@2240000 {
little-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
status = "disabled";
};
@ -263,11 +347,26 @@ i2c3: i2c@2030000 {
status = "disabled";
};
esdhc: esdhc@2140000 {
compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clock-frequency = <0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
status = "disabled";
};
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
dma-coherent;
status = "disabled";
};
};

3
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080a QDS Board.
*
* Copyright (C) 2015-17, Freescale Semiconductor
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>

3
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080a RDB Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>

2
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree file for Freescale LS2080a software Simulator model
*
* Copyright (C) 2014-2015, Freescale Semiconductor
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*

2
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright (C) 2014-2016, Freescale Semiconductor
* Copyright 2014-2016 Freescale Semiconductor, Inc.
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>

3
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2088A QDS Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*

3
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2088A RDB Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*

3
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -1,7 +1,8 @@
/*
* Device Tree Include file for Freescale Layerscape-2088A family SoC.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*

4
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080A QDS Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@ -45,6 +46,7 @@
*/
&esdhc {
mmc-hs200-1_8v;
status = "okay";
};

3
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
View File

@ -1,7 +1,8 @@
/*
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*

5
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -1,7 +1,8 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright (C) 2016-2017, Freescale Semiconductor
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
@ -471,7 +472,7 @@ esdhc: esdhc@2140000 {
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clock-frequency = <0>; /* Updated by bootloader */
clocks = <&clockgen 4 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;

71
arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi Normal file
View File

@ -0,0 +1,71 @@
/*
* QorIQ BMan Portals device tree
*
* Copyright 2011-2016 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
&bportals {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
bman-portal@0 {
/*
* bootloader fix-ups are expected to provide the
* "fsl,bman-portal-<hardware revision>" compatible
*/
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x4000000 0x4000>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x4010000 0x4000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x4020000 0x4000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@30000 {
compatible = "fsl,bman-portal";
reg = <0x30000 0x4000>, <0x4030000 0x4000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@40000 {
compatible = "fsl,bman-portal";
reg = <0x40000 0x4000>, <0x4040000 0x4000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@50000 {
compatible = "fsl,bman-portal";
reg = <0x50000 0x4000>, <0x4050000 0x4000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@60000 {
compatible = "fsl,bman-portal";
reg = <0x60000 0x4000>, <0x4060000 0x4000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@70000 {
compatible = "fsl,bman-portal";
reg = <0x70000 0x4000>, <0x4070000 0x4000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
};
bman-portal@80000 {
compatible = "fsl,bman-portal";
reg = <0x80000 0x4000>, <0x4080000 0x4000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
};
};

42
arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi Normal file
View File

@ -0,0 +1,42 @@
/*
* QorIQ FMan v3 10g port #0 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x90000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb0000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
pcsphy-handle = <&pcsphy6>;
};
mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
};
};

42
arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi Normal file
View File

@ -0,0 +1,42 @@
/*
* QorIQ FMan v3 10g port #1 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_rx_0x11: port@91000 {
cell-index = <0x11>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x91000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x31: port@b1000 {
cell-index = <0x31>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb1000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
pcsphy-handle = <&pcsphy7>;
};
mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
pcsphy7: ethernet-phy@0 {
reg = <0x0>;
};
};
};

41
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi Normal file
View File

@ -0,0 +1,41 @@
/*
* QorIQ FMan v3 1g port #0 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa8000 0x1000>;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-memac";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
};
mdio@e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};

41
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi Normal file
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@ -0,0 +1,41 @@
/*
* QorIQ FMan v3 1g port #1 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa9000 0x1000>;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-memac";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
};
mdio@e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};

41
arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi Normal file
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/*
* QorIQ FMan v3 1g port #2 device tree
*
* Copyright 2012-2015 Freescale Semiconductor Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
*/
fman@1a00000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-memac";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy2>;
};
mdio@e5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
pcsphy2: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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