powerpc/mm: Move hash specific pte width and other defines to book3s
This further make a copy of pte defines to book3s/64/hash*.h. This remove the dependency on pgtable-ppc64-4k.h and pgtable-ppc64-64k.h Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
3dfcb315d8
commit
ab537dca2f
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@ -1,4 +1,51 @@
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/* To be include by pgtable-hash64.h only */
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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/*
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* Entries per page directory level. The PTE level must use a 64b record
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* for each page table entry. The PMD and PGD level use a 32b record for
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* each entry by assuming that each entry is page aligned.
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*/
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#define PTE_INDEX_SIZE 9
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#define PMD_INDEX_SIZE 7
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#define PUD_INDEX_SIZE 9
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#define PGD_INDEX_SIZE 9
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PMD_SHIFT
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/* PUD_SHIFT determines what a third-level page table entry can map */
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#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PUD_SIZE (1UL << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
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#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS 0
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/* Bits to mask out from a PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0
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/* Bits to mask out from a PGD to get to the PUD page */
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#define PGD_MASKED_BITS 0
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/* PTE bits */
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#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
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@ -15,3 +62,40 @@
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/* shift to put page number into pte */
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#define PTE_RPN_SHIFT (17)
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#ifndef __ASSEMBLY__
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/*
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* 4-level page tables related bits
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*/
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#define pgd_none(pgd) (!pgd_val(pgd))
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#define pgd_bad(pgd) (pgd_val(pgd) == 0)
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#define pgd_present(pgd) (pgd_val(pgd) != 0)
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#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0)
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#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
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static inline pte_t pgd_pte(pgd_t pgd)
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{
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return __pte(pgd_val(pgd));
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}
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static inline pgd_t pte_pgd(pte_t pte)
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{
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return __pgd(pte_val(pte));
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}
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extern struct page *pgd_page(pgd_t pgd);
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#define pud_offset(pgdp, addr) \
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(((pud_t *) pgd_page_vaddr(*(pgdp))) + \
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(((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
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#define pud_ERROR(e) \
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pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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/*
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* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
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@ -1,4 +1,35 @@
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/* To be include by pgtable-hash64.h only */
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
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#include <asm-generic/pgtable-nopud.h>
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#define PTE_INDEX_SIZE 8
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#define PMD_INDEX_SIZE 10
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE 12
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Bits to mask out from a PMD to get to the PTE page */
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/* PMDs point to PTE table fragments which are 4K aligned. */
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#define PMD_MASKED_BITS 0xfff
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/* Bits to mask out from a PGD/PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0x1ff
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/* Additional PTE bits (don't change without checking asm in hash_low.S) */
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#define _PAGE_SPECIAL 0x00000400 /* software: special page */
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@ -74,8 +105,8 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_sub_valid(rpte, index) \
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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/* Trick: we set __end to va + 64k, which happens works for
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/*
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* Trick: we set __end to va + 64k, which happens works for
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* a 16M page as well as we want only one iteration
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*/
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#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
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@ -99,4 +130,13 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
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__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
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#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
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#define pte_pgd(pte) ((pgd_t)pte_pud(pte))
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */
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@ -5,11 +5,7 @@
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* the ppc64 hashed page table.
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*/
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/pgtable-ppc64-64k.h>
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#else
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#include <asm/pgtable-ppc64-4k.h>
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#endif
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#include <asm/book3s/64/hash.h>
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#include <asm/barrier.h>
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#define FIRST_USER_ADDRESS 0UL
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