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ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset 

DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2017-09-22 19:49:11 +03:00 committed by Vineet Gupta
parent edb40d74c0
commit ab8eb7db1d
2 changed files with 10 additions and 0 deletions
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9
arch/arc/boot/dts/hsdk.dts
View File

@ -12,6 +12,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/reset/snps,hsdk-reset.h>
/ { / {
model = "snps,hsdk"; model = "snps,hsdk";
@ -102,6 +103,12 @@ soc {
ranges = <0x00000000 0xf0000000 0x10000000>; ranges = <0x00000000 0xf0000000 0x10000000>;
cgu_rst: reset-controller@8a0 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8A0 0x4>, <0xFF0 0x4>;
};
core_clk: core-clk@0 { core_clk: core-clk@0 {
compatible = "snps,hsdk-core-pll-clock"; compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>, <0x14B8 0x4>; reg = <0x00 0x10>, <0x14B8 0x4>;
@ -158,6 +165,8 @@ ethernet@8000 {
clocks = <&gmacclk>; clocks = <&gmacclk>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";
phy-handle = <&phy0>; phy-handle = <&phy0>;
resets = <&cgu_rst HSDK_ETH_RESET>;
reset-names = "stmmaceth";
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;

1
arch/arc/configs/hsdk_defconfig
View File

@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_HSDK=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_TMPFS=y CONFIG_TMPFS=y