clk: bd718x7: Support ROHM BD71828 clk block
BD71828GW is a single-chip power management IC for battery-powered portable devices. Add support for controlling BD71828 clk using bd718x7 driver. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Matti Vaittinen
Lee Jones
parent
e795bf725d
commit
ae866dec74
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@ -305,10 +305,10 @@ config COMMON_CLK_MMP2
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Support for Marvell MMP2 and MMP3 SoC clocks
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config COMMON_CLK_BD718XX
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tristate "Clock driver for ROHM BD718x7 PMIC"
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depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
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tristate "Clock driver for 32K clk gates on ROHM PMICs"
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depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
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help
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This driver supports ROHM BD71837, ROHM BD71847 and
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This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
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ROHM BD70528 PMICs clock gates.
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config COMMON_CLK_FIXED_MMIO
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@ -7,12 +7,25 @@
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mfd/rohm-bd718x7.h>
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#include <linux/mfd/rohm-bd70528.h>
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#include <linux/mfd/rohm-generic.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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/* clk control registers */
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/* BD70528 */
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#define BD70528_REG_OUT32K 0x2c
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/* BD71828 */
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#define BD71828_REG_OUT32K 0x4B
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/* BD71837 and BD71847 */
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#define BD718XX_REG_OUT32K 0x2E
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/*
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* BD71837, BD71847, BD70528 and BD71828 all use bit [0] to clk output control
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*/
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#define CLK_OUT_EN_MASK BIT(0)
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struct bd718xx_clk {
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struct clk_hw hw;
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u8 reg;
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@ -21,10 +34,8 @@ struct bd718xx_clk {
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struct rohm_regmap_dev *mfd;
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};
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static int bd71837_clk_set(struct clk_hw *hw, int status)
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static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status)
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{
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status);
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}
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@ -33,14 +44,16 @@ static void bd71837_clk_disable(struct clk_hw *hw)
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int rv;
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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rv = bd71837_clk_set(hw, 0);
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rv = bd71837_clk_set(c, 0);
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if (rv)
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dev_dbg(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv);
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}
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static int bd71837_clk_enable(struct clk_hw *hw)
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{
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return bd71837_clk_set(hw, 1);
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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return bd71837_clk_set(c, 0xffffffff);
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}
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static int bd71837_clk_is_enabled(struct clk_hw *hw)
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@ -92,11 +105,15 @@ static int bd71837_clk_probe(struct platform_device *pdev)
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case ROHM_CHIP_TYPE_BD71837:
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case ROHM_CHIP_TYPE_BD71847:
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c->reg = BD718XX_REG_OUT32K;
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c->mask = BD718XX_OUT32K_EN;
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c->mask = CLK_OUT_EN_MASK;
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break;
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case ROHM_CHIP_TYPE_BD71828:
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c->reg = BD71828_REG_OUT32K;
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c->mask = CLK_OUT_EN_MASK;
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break;
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case ROHM_CHIP_TYPE_BD70528:
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c->reg = BD70528_REG_CLK_OUT;
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c->mask = BD70528_CLK_OUT_EN_MASK;
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c->reg = BD70528_REG_OUT32K;
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c->mask = CLK_OUT_EN_MASK;
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break;
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default:
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dev_err(&pdev->dev, "Unknown clk chip\n");
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@ -126,6 +143,7 @@ static const struct platform_device_id bd718x7_clk_id[] = {
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{ "bd71837-clk", ROHM_CHIP_TYPE_BD71837 },
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{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
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{ "bd70528-clk", ROHM_CHIP_TYPE_BD70528 },
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{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
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{ },
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};
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MODULE_DEVICE_TABLE(platform, bd718x7_clk_id);
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@ -89,10 +89,6 @@ struct bd70528_data {
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#define BD70528_REG_GPIO3_OUT 0x52
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#define BD70528_REG_GPIO4_OUT 0x54
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/* clk control */
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#define BD70528_REG_CLK_OUT 0x2c
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/* RTC */
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#define BD70528_REG_RTC_COUNT_H 0x2d
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@ -309,8 +305,6 @@ enum {
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#define BD70528_GPIO_IN_STATE_BASE 1
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#define BD70528_CLK_OUT_EN_MASK 0x1
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/* RTC masks to mask out reserved bits */
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#define BD70528_MASK_RTC_SEC 0x7f
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@ -183,9 +183,6 @@ enum {
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#define BD71828_REG_CHG_STATE 0x65
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#define BD71828_REG_CHG_FULL 0xd2
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/* CLK */
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#define BD71828_REG_OUT32K 0x4B
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/* LEDs */
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#define BD71828_REG_LED_CTRL 0x4A
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#define BD71828_MASK_LED_AMBER 0x80
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@ -417,7 +414,6 @@ enum {
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#define BD71828_INT_RTC1_MASK 0x2
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#define BD71828_INT_RTC2_MASK 0x4
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#define BD71828_OUT32K_EN 0x1
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#define BD71828_OUT_TYPE_MASK 0x2
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#define BD71828_OUT_TYPE_OPEN_DRAIN 0x0
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#define BD71828_OUT_TYPE_CMOS 0x2
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@ -191,12 +191,6 @@ enum {
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#define IRQ_ON_REQ 0x02
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#define IRQ_STBY_REQ 0x01
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/* BD718XX_REG_OUT32K bits */
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#define BD718XX_OUT32K_EN 0x01
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/* BD7183XX gated clock rate */
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#define BD718XX_CLK_RATE 32768
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/* ROHM BD718XX irqs */
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enum {
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BD718XX_INT_STBY_REQ,
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