drm/msm: dpu: Move DPU_POWER_HANDLE_DBUS_ID to core_perf
It's only used in core_perf, so stick it there (and change the name to reflect that). Changes in v2: - None Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Sean Paul
Rob Clark
parent
d53a61e1c0
commit
aeb7b49a1b
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@ -95,20 +95,20 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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memset(perf, 0, sizeof(struct dpu_core_perf_params));
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if (!dpu_cstate->bw_control) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
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1000ULL;
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perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
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}
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perf->core_clk_rate = kms->perf.max_core_clk_rate;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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perf->bw_ctl[i] = 0;
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perf->max_per_pipe_ib[i] = 0;
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}
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perf->core_clk_rate = 0;
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} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
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perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
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}
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@ -118,12 +118,12 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
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DPU_DEBUG(
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"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
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crtc->base.id, perf->core_clk_rate,
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
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perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
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perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MNOC],
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perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC],
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perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_LLCC],
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perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC],
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perf->max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_EBI],
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perf->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI]);
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}
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int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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@ -158,8 +158,8 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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/* obtain new values */
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_dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf);
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for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
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i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC;
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i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
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curr_client_type = dpu_crtc_get_client_type(crtc);
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@ -290,7 +290,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
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if (kms->perf.enable_bw_release) {
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trace_dpu_cmd_release_bw(crtc->base.id);
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DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id);
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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dpu_crtc->cur_perf.bw_ctl[i] = 0;
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_dpu_core_perf_crtc_update_bus(kms, crtc, i);
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}
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@ -367,7 +367,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
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new = &dpu_cstate->new_perf;
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if (_dpu_core_perf_crtc_is_power_on(crtc) && !stop_req) {
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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/*
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* cases for bus bandwidth update.
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* 1. new bandwidth vote - "ab or ib vote" is higher
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@ -409,13 +409,13 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
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update_clk = 1;
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}
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trace_dpu_perf_crtc_update(crtc->base.id,
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
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new->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI],
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new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MNOC],
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new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_LLCC],
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new->bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_EBI],
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new->core_clk_rate, stop_req,
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update_bus, update_clk);
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for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = 0; i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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if (update_bus & BIT(i)) {
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ret = _dpu_core_perf_crtc_update_bus(kms, crtc, i);
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if (ret) {
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@ -22,6 +22,19 @@
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#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
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/**
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* enum dpu_core_perf_data_bus_id - data bus identifier
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* @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
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*/
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enum dpu_core_perf_data_bus_id {
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DPU_CORE_PERF_DATA_BUS_ID_MNOC,
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DPU_CORE_PERF_DATA_BUS_ID_LLCC,
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DPU_CORE_PERF_DATA_BUS_ID_EBI,
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DPU_CORE_PERF_DATA_BUS_ID_MAX,
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};
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/**
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* struct dpu_core_perf_params - definition of performance parameters
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* @max_per_pipe_ib: maximum instantaneous bandwidth request
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@ -29,8 +42,8 @@
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* @core_clk_rate: core clock rate request
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*/
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struct dpu_core_perf_params {
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u64 max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MAX];
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u64 bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MAX];
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u64 max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MAX];
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u64 bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MAX];
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u64 core_clk_rate;
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};
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@ -1386,8 +1386,8 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
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seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
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seq_printf(s, "core_clk_rate: %llu\n",
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dpu_crtc->cur_perf.core_clk_rate);
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for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
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i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
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for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC;
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i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) {
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seq_printf(s, "bw_ctl[%d]: %llu\n", i,
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dpu_crtc->cur_perf.bw_ctl[i]);
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seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i,
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@ -27,19 +27,6 @@
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#define DPU_POWER_EVENT_DISABLE BIT(0)
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#define DPU_POWER_EVENT_ENABLE BIT(1)
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/**
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* enum DPU_POWER_HANDLE_DBUS_ID - data bus identifier
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* @DPU_POWER_HANDLE_DBUS_ID_MNOC: DPU/MNOC data bus
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* @DPU_POWER_HANDLE_DBUS_ID_LLCC: MNOC/LLCC data bus
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* @DPU_POWER_HANDLE_DBUS_ID_EBI: LLCC/EBI data bus
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*/
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enum DPU_POWER_HANDLE_DBUS_ID {
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DPU_POWER_HANDLE_DBUS_ID_MNOC,
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DPU_POWER_HANDLE_DBUS_ID_LLCC,
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DPU_POWER_HANDLE_DBUS_ID_EBI,
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DPU_POWER_HANDLE_DBUS_ID_MAX,
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};
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/*
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* struct dpu_power_event - local event registration structure
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* @client_name: name of the client registering
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