ARM: EXYNOS: add coupled cpuidle support for Exynos3250
The following patch adds coupled cpuidle support for Exynos3250 to an existing cpuidle-exynos driver. As a result it enables AFTR mode to be used by default on Exynos3250 without the need to hot unplug CPU1 first. The detailed changelog: - use exynos_[get,set]_boot_addr() in cpuidle-exynos.c and then make cpu_boot_reg_base() static - use exynos_core_restart() in exynos_cpu0_enter_aftr() - add missing smp_rmb() to exynos_cpu0_enter_aftr() (to make the code in-sync with the platform SMP code) - add call_firmware_op(cpu_boot, 1) to exynos_cpu0_enter_aftr() - use dsb_sev() instead of IPI wakeup for Exynos3250 in exynos_cpu0_enter_aftr() - add CPU0 vs CPU1 synchronization based on S5P_PMU_SPARE2 register for Exynos3250 to cpuidle-exynos.c - add flush_cache_all() for CPU1/0 before powerdown/AFTR for Exynos3250 to exynos_wfi_finisher()/exynos_do_idle() Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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@ -163,7 +163,9 @@ extern void exynos_set_delayed_reset_assertion(bool enable);
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extern void s5p_init_cpu(void __iomem *cpuid_addr);
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extern unsigned int samsung_rev(void);
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extern void __iomem *cpu_boot_reg_base(void);
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extern void exynos_core_restart(u32 core_id);
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extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
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extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
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static inline void pmu_raw_writel(u32 val, u32 offset)
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{
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@ -234,7 +234,8 @@ static void __init exynos_dt_machine_init(void)
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exynos_sysram_init();
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#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
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if (of_machine_is_compatible("samsung,exynos4210"))
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if (of_machine_is_compatible("samsung,exynos4210") ||
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of_machine_is_compatible("samsung,exynos3250"))
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exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
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#endif
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if (of_machine_is_compatible("samsung,exynos4210") ||
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@ -49,6 +49,7 @@ static int exynos_do_idle(unsigned long mode)
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sysram_ns_base_addr + 0x24);
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__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
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if (soc_is_exynos3250()) {
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flush_cache_all();
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exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
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SMC_POWERSTATE_IDLE, 0);
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exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
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@ -169,7 +169,7 @@ int exynos_cluster_power_state(int cluster)
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S5P_CORE_LOCAL_PWR_EN);
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}
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void __iomem *cpu_boot_reg_base(void)
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static void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM5;
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@ -195,7 +195,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
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*
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* Currently this is needed only when booting secondary CPU on Exynos3250.
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*/
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static void exynos_core_restart(u32 core_id)
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void exynos_core_restart(u32 core_id)
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{
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u32 val;
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@ -247,7 +247,7 @@ static void exynos_secondary_init(unsigned int cpu)
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spin_unlock(&boot_lock);
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}
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static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
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int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
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{
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int ret;
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@ -272,7 +272,7 @@ static int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
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return ret;
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}
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static int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
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int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
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{
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int ret;
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@ -22,6 +22,7 @@
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#include <asm/firmware.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <asm/cacheflush.h>
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#include <mach/map.h>
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@ -209,6 +210,8 @@ static int exynos_cpu0_enter_aftr(void)
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* sequence, let's wait for one of these to happen
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*/
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while (exynos_cpu_power_state(1)) {
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unsigned long boot_addr;
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/*
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* The other cpu may skip idle and boot back
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* up again
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@ -221,7 +224,11 @@ static int exynos_cpu0_enter_aftr(void)
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* boot back up again, getting stuck in the
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* boot rom code
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*/
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if (__raw_readl(cpu_boot_reg_base()) == 0)
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ret = exynos_get_boot_addr(1, &boot_addr);
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if (ret)
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goto fail;
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ret = -1;
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if (boot_addr == 0)
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goto abort;
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cpu_relax();
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@ -233,11 +240,14 @@ static int exynos_cpu0_enter_aftr(void)
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abort:
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if (cpu_online(1)) {
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unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
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/*
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* Set the boot vector to something non-zero
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*/
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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cpu_boot_reg_base());
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ret = exynos_set_boot_addr(1, boot_addr);
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if (ret)
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goto fail;
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dsb();
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/*
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@ -247,22 +257,42 @@ static int exynos_cpu0_enter_aftr(void)
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while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
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cpu_relax();
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if (soc_is_exynos3250()) {
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while (!pmu_raw_readl(S5P_PMU_SPARE2) &&
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!atomic_read(&cpu1_wakeup))
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cpu_relax();
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if (!atomic_read(&cpu1_wakeup))
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exynos_core_restart(1);
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}
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while (!atomic_read(&cpu1_wakeup)) {
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smp_rmb();
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/*
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* Poke cpu1 out of the boot rom
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*/
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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cpu_boot_reg_base());
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arch_send_wakeup_ipi_mask(cpumask_of(1));
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ret = exynos_set_boot_addr(1, boot_addr);
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if (ret)
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goto fail;
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call_firmware_op(cpu_boot, 1);
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if (soc_is_exynos3250())
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dsb_sev();
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else
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arch_send_wakeup_ipi_mask(cpumask_of(1));
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}
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}
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fail:
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return ret;
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}
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static int exynos_wfi_finisher(unsigned long flags)
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{
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if (soc_is_exynos3250())
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flush_cache_all();
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cpu_do_idle();
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return -1;
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@ -283,6 +313,9 @@ static int exynos_cpu1_powerdown(void)
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*/
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exynos_cpu_power_down(1);
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if (soc_is_exynos3250())
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pmu_raw_writel(0, S5P_PMU_SPARE2);
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ret = cpu_suspend(0, exynos_wfi_finisher);
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cpu_pm_exit();
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@ -299,7 +332,9 @@ static int exynos_cpu1_powerdown(void)
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static void exynos_pre_enter_aftr(void)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base());
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unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
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(void)exynos_set_boot_addr(1, boot_addr);
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}
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static void exynos_post_enter_aftr(void)
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