arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block
Remove register information used to reset and enable/disable clock for AHB block as reseting AHB or disabling its clock will make other peripherals attached to it stop working. Signed-off-by: Duc Dang <dhdang@apm.com>
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@ -140,17 +140,12 @@ socplldiv2: socplldiv2 {
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clock-output-names = "socplldiv2";
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clock-output-names = "socplldiv2";
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};
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};
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ahbclk: ahbclk@1f2ac000 {
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ahbclk: ahbclk@17000000 {
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compatible = "apm,xgene-device-clock";
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f2ac000 0x0 0x1000
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reg = <0x0 0x17000000 0x0 0x2000>;
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0x0 0x17000000 0x0 0x2000>;
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reg-names = "div-reg";
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reg-names = "csr-reg", "div-reg";
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csr-offset = <0x0>;
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csr-mask = <0x1>;
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enable-offset = <0x8>;
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enable-mask = <0x1>;
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divider-offset = <0x164>;
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divider-offset = <0x164>;
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divider-width = <0x5>;
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divider-width = <0x5>;
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divider-shift = <0x0>;
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divider-shift = <0x0>;
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@ -150,17 +150,12 @@ socplldiv2: socplldiv2 {
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clock-output-names = "socplldiv2";
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clock-output-names = "socplldiv2";
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};
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};
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ahbclk: ahbclk@1f2ac000 {
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ahbclk: ahbclk@17000000 {
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compatible = "apm,xgene-device-clock";
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f2ac000 0x0 0x1000
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reg = <0x0 0x17000000 0x0 0x2000>;
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0x0 0x17000000 0x0 0x2000>;
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reg-names = "div-reg";
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reg-names = "csr-reg", "div-reg";
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csr-offset = <0x0>;
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csr-mask = <0x1>;
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enable-offset = <0x8>;
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enable-mask = <0x1>;
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divider-offset = <0x164>;
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divider-offset = <0x164>;
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divider-width = <0x5>;
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divider-width = <0x5>;
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divider-shift = <0x0>;
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divider-shift = <0x0>;
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