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ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes 

This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Gregory CLEMENT 2018-03-14 17:19:28 +01:00
parent ef04faf106
commit b15c9d3550
1 changed files with 6 additions and 3 deletions
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9
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
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@ -433,7 +433,8 @@ CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 13>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
@ -460,7 +461,8 @@ CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 11>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
@ -487,7 +489,8 @@ CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&CP110_LABEL(clk) 1 12>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
status = "disabled";
};
};