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defxx: DEFEA's Burst Holdoff register initialization fix 

Use the mask rather than bit number macro to initialize the chip select
control bit for PDQ register space decoding in the Burst Holdoff register.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Maciej W. Rozycki 2014-09-25 11:06:45 +01:00 committed by David S. Miller
parent 8a189f1288
commit b1a6d3ecf8
1 changed files with 2 additions and 2 deletions
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4
drivers/net/fddi/defxx.c
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@ -748,9 +748,9 @@ static void dfx_bus_init(struct net_device *dev)
*/
val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
if (dfx_use_mmio)
val |= PI_BURST_HOLDOFF_V_MEM_MAP;
val |= PI_BURST_HOLDOFF_M_MEM_MAP;
else
val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;
outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);
/* Enable interrupts at EISA bus interface chip (ESIC) */