p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge remote-tracking branch 'asoc/topic/doc' into asoc-next

This commit is contained in:
Mark Brown 2015-10-26 11:15:57 +09:00
parent 12e7b4a4f3 1d387a3fd8
commit b27aafedfd
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
include/sound/soc-dai.h
View File

@ -48,10 +48,25 @@ struct snd_compr_stream;
#define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */ #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
/* /*
* DAI hardware signal inversions. * DAI hardware signal polarity.
* *
* Specifies whether the DAI can also support inverted clocks for the specified * Specifies whether the DAI can also support inverted clocks for the specified
* format. * format.
*
* BCLK:
* - "normal" polarity means signal is available at rising edge of BCLK
* - "inverted" polarity means signal is available at falling edge of BCLK
*
* FSYNC "normal" polarity depends on the frame format:
* - I2S: frame consists of left then right channel data. Left channel starts
* with falling FSYNC edge, right channel starts with rising FSYNC edge.
* - Left/Right Justified: frame consists of left then right channel data.
* Left channel starts with rising FSYNC edge, right channel starts with
* falling FSYNC edge.
* - DSP A/B: Frame starts with rising FSYNC edge.
* - AC97: Frame starts with rising FSYNC edge.
*
* "Negative" FSYNC polarity is the one opposite of "normal" polarity.
*/ */
#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */