drm/amd/powerplay: fix mclk in high clock for baffin
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1377,13 +1377,14 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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result = polaris10_populate_single_memory_level(hwmgr,
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result = polaris10_populate_single_memory_level(hwmgr,
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dpm_table->mclk_table.dpm_levels[i].value,
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dpm_table->mclk_table.dpm_levels[i].value,
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&levels[i]);
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&levels[i]);
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if (i == dpm_table->mclk_table.count - 1) {
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levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
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levels[i].EnabledForActivity = 1;
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}
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if (result)
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if (result)
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return result;
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return result;
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}
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}
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/* Only enable level 0 for now. */
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levels[0].EnabledForActivity = 1;
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/* in order to prevent MC activity from stutter mode to push DPM up.
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/* in order to prevent MC activity from stutter mode to push DPM up.
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* the UVD change complements this by putting the MCLK in
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* the UVD change complements this by putting the MCLK in
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* a higher state by default such that we are not effected by
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* a higher state by default such that we are not effected by
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@ -1396,9 +1397,6 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
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(uint8_t)dpm_table->mclk_table.count;
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(uint8_t)dpm_table->mclk_table.count;
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data->dpm_level_enable_mask.mclk_dpm_enable_mask =
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data->dpm_level_enable_mask.mclk_dpm_enable_mask =
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phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
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phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
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/* set highest level watermark to high */
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levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
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PPSMC_DISPLAY_WATERMARK_HIGH;
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/* level count will send to smc once at init smc table and never change */
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/* level count will send to smc once at init smc table and never change */
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result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
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result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
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