pwm: rcar: Improve calculation of divider
The rcar_pwm_get_clock_division() has a loop to calculate the divider, but the value of div should be calculatable without a loop. So, this patch improves it. This algorithm is suggested by Uwe Kleine-König and Laurent Pinchart. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -8,6 +8,8 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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@ -68,19 +70,15 @@ static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
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static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
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{
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unsigned long clk_rate = clk_get_rate(rp->clk);
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unsigned long long max; /* max cycle / nanoseconds */
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unsigned int div;
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u64 div, tmp;
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if (clk_rate == 0)
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return -EINVAL;
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for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) {
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max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE *
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(1 << div);
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do_div(max, clk_rate);
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if (period_ns <= max)
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break;
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}
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div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
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tmp = (u64)period_ns * clk_rate + div - 1;
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tmp = div64_u64(tmp, div);
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div = ilog2(tmp - 1) + 1;
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return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
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}
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