ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -193,6 +193,7 @@ pcie1_rc: pcie@51000000 {
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 1>,
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<0 0 0 2 &pcie1_intc 2>,
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@ -218,6 +219,7 @@ pcie1_ep: pcie_ep@51000000 {
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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status = "disabled";
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};
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};
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