ARM: dts: dra7: Add properties to enable PCIe x2 lane mode

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kishon Vijay Abraham I 2019-03-25 15:15:25 +05:30 committed by Tony Lindgren
parent 9e98c678c2
commit b5acec09e2
1 changed files with 2 additions and 0 deletions

View File

@ -193,6 +193,7 @@ pcie1_rc: pcie@51000000 {
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 1>,
<0 0 0 2 &pcie1_intc 2>,
@ -218,6 +219,7 @@ pcie1_ep: pcie_ep@51000000 {
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
status = "disabled";
};
};