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RDMA/hns: Add sq_invld_flg field in QP context 

In hip08 RoCE, it need to add the sq_invld_flg field
in QP context for RoCE hardware.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Yixian Liu <liuyixian@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
oulijun 2017-11-10 16:55:50 +08:00 committed by Doug Ledford
parent 2872646134
commit b5fddb7ce7
2 changed files with 6 additions and 2 deletions
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2
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View File

@ -2042,6 +2042,8 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
roce_set_bit(qpc_mask->byte_168_irrl_idx, roce_set_bit(qpc_mask->byte_168_irrl_idx,
V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
roce_set_bit(qpc_mask->byte_168_irrl_idx,
V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
roce_set_field(qpc_mask->byte_168_irrl_idx, roce_set_field(qpc_mask->byte_168_irrl_idx,
V2_QPC_BYTE_168_IRRL_IDX_LSB_M, V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);

6
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
View File

@ -606,8 +606,10 @@ struct hns_roce_v2_qp_context {
#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
#define V2_QPC_BYTE_168_LP_SGEN_INI_S 21 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 21)
#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24) #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)