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dt-bindings: socfpga-dwmac: add "altr, socfpga-stmmac-a10-s10" binding 

Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10
implementation of the stmmac ethernet controller.

On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from
the Cyclone5 and Arria5:
     - The emac PHY setup bits are in separate registers.
     - The PTP reference clock select mask is different.
     - The register to enable the emac signal from FPGA is different.

Because of these differences, the dwmac-socfpga glue logic driver will
use this new binding to set the appropriate bits for PHY, PTP reference
clock, and signal from FPGA.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dinh Nguyen 2019-06-05 10:05:50 -05:00 committed by David S. Miller
parent 020aa5c7d4
commit b637e0856a
1 changed files with 8 additions and 2 deletions
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10
Documentation/devicetree/bindings/net/socfpga-dwmac.txt
View File

@ -6,11 +6,17 @@ present in Documentation/devicetree/bindings/net/stmmac.txt.
The device node has additional properties: The device node has additional properties:
Required properties: Required properties:
- compatible : Should contain "altr,socfpga-stmmac" along with - compatible : For Cyclone5/Arria5 SoCs it should contain
"snps,dwmac" and any applicable more detailed "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
"altr,socfpga-stmmac-a10-s10".
Along with "snps,dwmac" and any applicable more detailed
designware version numbers documented in stmmac.txt designware version numbers documented in stmmac.txt
- altr,sysmgr-syscon : Should be the phandle to the system manager node that - altr,sysmgr-syscon : Should be the phandle to the system manager node that
encompasses the glue register, the register offset, and the register shift. encompasses the glue register, the register offset, and the register shift.
On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
on the Arria10/Stratix10/Agilex platforms, the register shift represents
bit for each emac to enable/disable signals from the FPGA fabric to the
EMAC modules.
- altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
for ptp ref clk. This affects all emacs as the clock is common. for ptp ref clk. This affects all emacs as the clock is common.